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eMMC 5.0 Memory Model

Specification Support

Supports the eMMC 5.0 and 5.1 specification

Product Highlights

General model features
Common queuing
Enhanced strobe in HS400 mode
Cache barrier
CID/CSD/OCR/Ext_CSD registers Implements register bit definitions for a subset of eMMC standard bit definitions.
High capacity negotiation For devices larger than 2GB, the addressing mechanism is switched from byte addressing to sector addressing.
Initialization checks Checks for proper initialization sequence. This check can be skipped.
Supports eMMC command/response protocol Implements 48 bit input command format and R1, R1b, R2, etc. response formats.
State machine and timing checks Implements internal eMMC state machine and performs specified timing checks.
Voltage range checking As part of the CMD1 operation, the model will implement voltage range negotiation.
Background operation control  
Cache command Implements Cache Read/Write operations per the eMMC JEDEC specification
Context IDs Implements the Context Management functionality per the eMMC JEDEC spec
Data tag mechanism Implements Data tag mechanism per eMMC JEDEC spec.
DDR timing Supports Dual Data Rate timing mode for Read/Write operations, reading CID and CSD registers, sending CRC status and Boot acknowledge
Discard command Implements Discard operation per eMMC JEDEC spec
Extended partition types Implements Extended Partition Types operation per eMMC JEDEC spec.
High speed 200MHz mode Implements 200 MB/s Read/Write operation
HPI Supports High Priority Interrupt mechanism
Large(4Kb) sector size Implements Read/Write operations for large 4Kb sector sizes
Packed commands Implements Packed Read/Write operation per eMMC JEDEC spec.
Power Off Notification Supports notification mechanism when the host intends to power off the device
Real Time Clock Supports accepting Real Time Clock Information the host sends to the card
RPMB Implements Replay Protected Memory Block functionality per the eMMC JEDEC spec
Sanitize command

Implements Sanitize operation per eMMC JEDEC spec.

High-Speed 400 Implements HS400 Dual Data Rate Read and Write interface per eMMC 5.0 JEDEC spec.
Data Strobe Added a new signal "Data Strobe" which directs bit transfer on data lines in HS400 mode.
Command Queuing Added support for the command queuing feature per the eMMC 5.1 specification.