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Memory Model for DDR5 RDIMM

Description

The Cadence® Verification IP (VIP) for DDR5 RDIMM provides support for the JEDEC® DDR5 SDRAM Registered DIMM Design Specification, DDR5 RDIMM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 RDIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR5 RDIMM is the next-generation DIMM specification with improvements in the areas of speed, configurability, reliability, and power saving. It supports speeds up to 4400 speed grade.

 

Specification Support

The Memory Model for DDR5 RDIMM is evolving and supports the proposals that are balloted at JEDEC. The latest ballots/specifications are available at http://www.jedec.org.

 


RELEASE
STANDARD
VIPCAT 11.3.051

Evolving

 

Key Features

Feature Name
Description

DIMM types

DDR5 UDIMM, RDIMM

DIMM configuration support

Supports up to 2 ranks

Supports dual independent channels

ECC checks bits

Can optionally have a DRAM instantiation for checks bits.

Core RCD forwarding logic 

All DRAM Commands.

RCD Data Rate

Supports DDR , SDR1, SDR2 Modes

Parity

Supports optionally checking for even parity. In case of errors : Gate DRAM commands.

DRAM Features

Refer to the DDR5 SDRAM page

 

Other Supported Features


FEATURE NAME
DESCRIPTION

Methodologies

Unified Verification Methodology (UVM), OVM

Simulators

IES, VCS, and MTI

Testbench Language Interfaces

Verilog, VHDL, SystemVerilog, e and SystemC

Trace Debug

Yes