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Memory Model for GDDR6

Description  

This Cadence® Verification IP (VIP) provides support for the JEDEC® Graphics Double Data Rate (GDDR6) SGRAM GDDR6 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for GDDR6 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

The GDDR6 standard is a modern type of synchronous graphics random-access memory (SGRAM) with a high bandwidth ("double date rate") interface designed for use in graphics cards, game consoles and high-performance computation.

Specification

The VIP for GDDR6 Memory Model is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at http://www.jedec.org.

Protocol Features  

Key features of the GDDR6 device standard supported by the Cadence GDDR6 VIP are listed below:

Feature Name

Description

Bank Architecture

8B, 16B, and 2BankGroup supported.

General GDDR6 functionality

Command decoding and related error conditions

Clock

CK (DDR)

WCK (DDR, QDR)

Supported Commands

Refresh all banks (REFab) 

Activate (ACT)

Write without mask (WOM)

Write without mask with autoprecharge (WOMA)

Read (RD) 

Read with autoprecharge (RDA)

Precharge all banks (PREab)

Precharge per bank (PREpb)

No operation (NOP)

Initialization

Power-up sequence

Interface Trainings

Command address training

WCK2CK training

Read training

Write training

Mode registers

Supports register functionality.

Command Address Bus Inversion (CABI)

The number of CA lines driving a LOW level can be limited to 5 in 2 channel mode or 7 in PC mode for 8 Gb, 12 Gb and 16 Gb densities and limited to 6 in 2 channel mode or 8 in PC mode for 24 Gb and 32 Gb densities

Data Bus Inversion (DBI)

Data on the bus can be inverted during both read and write to save power. Data Bus Inversion the feature can be set through mode register.

Device density

Supports a wide range of device densities from 2Gb to 32Gb.

Latency code frequency table

Supports and checks all read and write latency requirements for a given frequency.

Tccd+n Reads and Writes

Supports all combinations of Reads merging and Writes merging placed Tccd+n apart.

Key Verification Capabilities

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Ability to dynamically change the timing parameter
  • Ability to check for errors and change error severity
  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)
  • Registers to indicate the model state, bank state and initialization state
  • Initialization can be optionally skipped
  • UVM Configuration: Users can configure the VIP agent using the UVM config class
  • Functional coverage