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LRDIMM Memory Model

Specification Support

DDR RDIMM Memory Model VIP supports JEDEC DDR3 SDRAM Registered DIMM Design Specification Revision 0.84, as well as LRDIMM Specification Memory Buffer (Rev 0.95a) and JEDEC DDR3 Register - JESD82-29A for SSTE32882 (the RCD) specification.

Key Features

Feature Name
Weak driver support Added support for pull up/down and weak drivers for inout signals

Configurable DIMM topology

Number of ranks and components constituting the DIMM are configurable using SOMA files.
Flyby delays Supports of fly by delays DIMM to DRAM (for UDIMM) and RCD to DRAM (for RDIMM/LRDIMM).
ECC checks bits A DRAM instantiation for checks bits is optionally available.
Address Mirroring RDIMM will optionally mirror address bits (as mentioned in the specification).
Init and Reset Models both the Power Up Reset and Reset with Stable Power with all timing and pin validity checks.
Core RCD forwarding logic DRAM MRS command handling, Inversion, Mirroring, Command Latency, propagation delay, gating with parity checks, different CS modes, etc.
RCD Control Word Writes Controller can do CWW and set bits to change most of the control word settings.
Parity Supports optional checking for even parity in case of errors gating CWW and DRAM commands defined in the spec.
DRAM Features Refer to the DDR2/DDR3 SDRAM page