This Cadence® Verification IP (VIP) supports the JEDEC® Low-Power Memory Device, LPDDR5 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for LPDDR5 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The LPDDR5 standard is an industry-leading low-power volatile (DRAM) device memory standard for storage of system code, software applications, and user data. The LPDDR5 Low-Power Memory Device Standard is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks, and similar connected devices on the newest, high-speed 4G networks.


The VIP for LPDDR5 Memory Model is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at http://www.jedec.org.

  • JESD209-5A
  • JC-42.6-1854.99A dated 2019/10/04

Protocol Features

Key features of the LPDDR5 device standard supported by the Cadence VIP for LPDDR5 are listed below:

Feature Name

Bank Architecture

8B, 16B, and 4BankGroup supported.

General DDR Functionality

  • Command Decoding and related error conditions 
  • Activation, Precharge, and Mode Register Write and Read, CAS, Mask Write, Read, Write, Mask Write, Power Down, Refresh, Self Refresh, and DSM command and related timing checks
  • Core timing
  • Initialization Sequence
  • Bus timing (Setup/Hold(Per Lane or Per Bit), Pulse width)
  • Clock frequency change and clock stop and related checkers.
  • RDQS timing support
  • VREF Current Generator (VRCG)
  • Differential Clock (CK, WCK) checks
  • Duty Cycle Monitor (DCM)
  • Temperature Derating
  • Core timing table when Link ECC is enabled 
  • The user configurable timing parameters to corrupt data eye during Read Path


1066.5MHz (8533 Mbps)

Training Modes

  • Enhanced RDQS training mode
  • Read DQ Calibration
  • Write Leveling
  • Command Bus Training Mode 1 and Mode2
  • WCK2DQ oscillator
  • RDQS toggle mode
  • Read FIFO and Write FIFO 
  • Link ECC WCK-RDQS_t/Parity Training using FIFO
  • Vref CA training
  • Vref DQ training
  • Read/Write based WCK-RDQS_t Training

Write Clock

  • WCK2Ck synchronization
  • 4:1 and 2:1 WCK to CK ratio
  • WCK Sync off timing
  • WCK2DQ AC timings for low and high frequency
  • Enhanced WCK always On
  • Write clock-related timing parameter support - tWCH, tWCL, tWCK(avg), and tJIT
  • WCK suspend mode - tWCKSUS

Low Power Consumption Features

  • Read and Write Datacopy
  • Write-X
  • WXS, WXSA, and WXSB support (byte controllable writex) 

Mode Registers

Register functionality

Configurable Preamble and Postamble

Allows preamble and postamble to be configured for Read, Write and Mask Write

Data Bus Inversion

Data on the bus can be inverted during both read and write to save power. Data Bus Inversion the feature can be set through mode register

Device Density

Supports a wide range of device densities from 2Gb to 32Gb

Frequency Set Points    

Allows LPDDR5 to be switched between two different operating frequencies by duplicating mode register parameters commonly changed with operating frequency

Exploration Mode

Model acts as a passive monitor in exploration mode. This means only command and clock needs to fed to the model and rest of pins such as WCK, RDQS, DQ, and DMI need not be connected. The model only checks for command protocol and does not drive data. There is no activity on the data bus but all other command spacing are supported. At present, Model is supporting exploration mode forRead, MRR, Write, and Mask Write commands.

Multipurpose Command (MPC)

Supports all 6 MPC commands

Command Bus Training    

The training centers the internal VREF(ca) in the CA data eye and, at the same time, allows for timing adjustments of the CS and CA signals to meet setup and hold requirements

Latency Code Frequency Table

Supports and checks all read and write latency requirements for a given frequency

Tccd+n Reads and Writes

Supports all combinations of Reads merging and Writes merging placed Tccd+n apart

Delay Modeling

Delay modeling of input and output signals, display of delay modeling internal signals on the simulator waveform

Single-Ended Clock

Single-Ended Clock, Write Clock, and RDQS support

Byte Mode (x8)

Support for Byte Mode devices


Refresh rates and options to control the application of new rates

Temperature Derating

Support for temperature derating and per-timing derating factor

Link Error Correcting Code (Link-ECC)

Support for Write and Read Link ECC

DMI Pin Behavior

DMI Pin behavior based on Read/Write-related commands

On Die Termination (ODT)

Support for ODT on timings, which is command-to-command timing checks with ODT enabled, tODTup, tDQ7FSP

ZQ Calibration (ODT)

Support for command based and background ZQ calibration

Skew Support

Support for adding skew on RDQS using tDQSQ
Support for adding skew on bytelane during Write using tWCKDQISkew

Duty Cycle Adjuster

Support for controlling the duty cycle of RDQS/DQ during Reads

Rank to Rank Timing Checks

Support for rank2rank timing checks using LPDDR5MDP (Multi Package DRAM)
Support includes all the Rank-to-Rank timing constraints available in JESD209-5A spec

Refresh Management

Support for Refresh Management functionality

Monitor Mode

In this mode, the DRAM will perform all functions (Complete Protocol validation), however, the DRAM will not drive (output) any data on I/O pins, you can say that model is enabled in passive mode where it will validate all bus activities

Decision Feedback Equalization (DFE)

Support for DFE includes

  • Rank to rank timing constraints affected with enabling DFE
  • tDPRE pre-drive requirement before the write data burst operation

Functional Coverage

Provides a rich functional coverage of the model
Inter-rank timing checks coverage is provided with LPDDR5MDP (Multi Package DRAM)

Delay Randomization

Support for delay randomization on WCKDQO with drifts


Support Post Package Repair functionality

Key Verification Capabilities

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory

  • Ability to dynamically change the timing parameter

  • Ability to check for errors and change error severity

  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)

  • Registers to indicate the model state, bank state, and initialization state

  • Initialization can be optionally skipped

  • UVM Configuration: Users can configure the VIP agent using the UVM config class

  • Functional coverage

  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker

See the Verification IP Support Home for more information.