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LPDDR5 Memory Model

This Cadence® Verification IP (VIP) provides support for the JEDEC® Low-Power Memory Device, LPDDR5 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for LPDDR5 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

The LPDDR5 standard is an industry-leading low-power volatile (DRAM) device memory standard for storage of system code, software applications, and user data. The LPDDR5 Low-Power Memory Device Standard is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks, and similar connected devices on the newest, high-speed 4G networks.


The VIP for LPDDR5 Memory Model is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at http://www.jedec.org.

JEDEC Standard
VIPCAT 11.3.051

LPDDR5 Specification Draft_R09_r2


Protocol Features

Key features of the LPDDR5 device standard supported by the Cadence VIP are listed below:

Feature Name

Bank Architecture

8B, 16B and 4BankGroup supported.

General DDR functionality

  • Command Decoding and related error conditions 

  • Activation, Precharge, and Mode Register Write/Read, and Mask Write

  • Latency Table

  • Basic Write and Reads. New WCK based implementation is supported

  • 4:1 and 2:1 WCK to CK ratio

  • Refresh, Power Down, Self Refresh and Deep Sleep Mode

  • Core Timing

  • Initialization Sequence

  • Basic support for Read FIFO and Write FIFO 

  • Basic support for Read DQ Calibration and Write Leveling

  • Basic support for CA training Mode1 and Mode2

  • tCSLCK, tCKCSH timing parameters

  • Bus timing (setup, hold)

Mode registers

Supports register functionality.

Data Bus Inversion

Data on the bus can be inverted during both read and write to save power. Data Bus Inversion feature can be set through mode register.

Device density

Supports a wide range of device densities from 2Gb to 32Gb.

Frequency set points    

Allows LPDDR5 to be switched between two differing operating frequencies by duplicating mode register parameters commonly changed with operating frequency.

Exploration Mode

Model acts as a passive monitor in exploration mode.

This means only command and clock needs to fed to the model and rest of pins like WCK, RDQS, DQ, DMI etc. need not be connected.

Model only checks for command protocol and does not drive data. There is no activity on the data bus but all other command spacing, etc., are supported.

At present, Model is supporting exploration mode for Read, MRR, Write, and Mask Write commands.


Key Verification Capabilities 

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Ability to dynamically change timing parameter
  • Error checking 
  • Transaction and memory callbacks for all protocol and device memory events (Read/Write)
  • Registers to indicate the model state, bank state and initialization state
  • Initialization can be optionally skipped
  • UVM Configuration: Users can configure the VIP agent using the UVM config class


Other Supported Features

Methodologies Unified Verification Methodology (UVM), OVM
Simulators IES, VCS, and MTI
Testbench Language Interfaces Verilog, VHDL, SystemVerilog, e and SystemC
Trace Debug Yes