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LPDDR4 Memory Model

Specification Support

The LPDDR4 Memory Model VIP is evolving and supports the most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available here: http://www.jedec.org

Key Features

Feature Name

 Description

Dual channels Support 2 channels which can function independently

General DDR functionality and timing checks

Precharge, Activate, Read, Write, Mask Write, Mode Register Read, Mode Register Write, Power Down,Refresh, Self Refresh and related timing checks

Device density

Supports a wide range of device densities  from 4Gb to 32 Gb

Speed (Mt/s) 2133 MHz (4266 MT/s)
Data Mask and Data Bus Inversion Data on the bus can be inverted during both read and write to save power. Both Data Mask and Data Bus inversion features can be set through mode registers
On the fly burst length Bust length during Read, Write and Mask Write can be set on the fly through command data and mode registers
Configurable preamble and postamble Allows  preamble and postamble to be configured for Read, Write and Mask Write
Frequency set points    

Allows LPDDR4 to be switched between two differing operating frequencies by duplicating mode register parameters commonly changed with operating frequency

FIFO register and DQS-DQ training Supports Read FIFO and Write FIFO commands used during Write training
Multipurpose Command (MPC) Supports all 7 MPC commands
Command bus training    

The training centers the internal VREF(ca) in the CA data eye and, at the same time, allows for timing adjustments of the CS and CA signals to meet setup/hold requirements.

Latency code frequency table Supports and checks all read and write latencies requirements for a given frequency
Vref settings             Support CA and DQ voltage reference settings
Tccd+n Reads/Writes Supports all combinations of Reads merging and Writes merging placed Tccd+n apart