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LPDDR3 Memory Model

Specification Support

The LPDDR3 Memory Model VIP supports the officially released JESD209-3 version of the LPDDR3 specification. The specification is available here: http://www.jedec.org/sites/default/files/docs/JESD209-3.pdf

Key Features

Feature Name

 Description

General DDR functionality and timing checks

Pre-charge, Activate, Read, Write, Mode Register Write, Power Down, Deep Power Down, Self Refresh, Initializations and all related timing checks.

Device temperature sensor

This sensor can be used to determine an appropriate refresh rate, determine whether AC timing de-rating is required in the elevated temperature range, and/or monitor the operating temperature

Device density support

LPDDR3 supports a wide range of device densities from 4Gb to 32 Gb

On-die termination (ODT) Enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation and pin count
Partial-array self refresh and per-bank refresh Allows portions of the array to be powered down when not required, permitting applications to determine device memory requirements on a real-time usage basis
Write-leveling and CA training Allow the memory controller to compensate for signal skew, ensuring that data input setup and hold timing as well as command and address input timing requirements are met while operating at the industry’s fastest input bus speeds