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DDR5 Memory Model

This Cadence® Verification IP (VIP) supports the JEDEC® Memory Device DDR5 SDRAM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for DDR5 SDRAM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The DDR5 standard is the next generation of DRAM device memory standard with many improvements in performance, reliability, and power saving over the previous generation of DRAM devices (DDR4). DDR5 addresses industry demand with increased bandwidth, capacity, power-saving features, and with more reliability through CRC and ECC.

Specification Support

The Memory Model VIP for DDR5 SDRAM is evolving and current implementation is based on the following task groups.

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
General DDR functionality and timing checks
  • Reset
  • Initialization 
  • Mode Register Write 
  • Mode Register Read 
  • Prechange
  • Precharge Same Bank 
  • Precharge All Bank
  • Activate
  • Read
  • Write
  • MPC
  • Write Data Pattern and Refresh command
  • Bus timing (setup, hold and pulse width checks)
  • Protocol checks associated with all these commands
  • ODT(Partial Support)
  • Power Down Mode
  • Self Refresh Mode
  • Speed bin checks(Partial Support)
  • CS Training Mode
  • CA Training Mode
  • Write Leveling
Latest Command Decoding Single-cycle and two-cycle commands with support for both targeted and non-targeted commands, 1N/2N Mode Support
Data Width

x4, x8

Density 8 Gb, 16 Gb, 24 Gb, 32 Gb
Configurations CL, CWL, AL, Burst Type, Burst Length, Write Data pattern

3200, 3600, 4000, 4400

Bank Groups 8 or 4 bank groups. Modeling the concept and the timing associated with the back-to-back accesses to the same and difference bank group.
Refresh options 1x refresh mode, 2x refresh mode


Key Verification Capabilities

  • Back Door Accesses to mode registers and device memory
  • Ability to dynamically change timing parameter
  • Callbacks: Detailed stranded out assertions for JESD79-4 specified checks with assertion coverage tracking and configurable message severity.
  • Memory and and transaction callbacks for reads and writes. Transaction callbacks for all other commands.
  • Transaction protocol callbacks during command execution, data pass, and errors reporting – for connecting user testbench scoreboard and reference model. Also has ability to modify some fields to cause error injection (not in Verilog).
  • Similar callback notifications to testbench on initialization, bank and model state changes, and as mode register changes. Alternatively, the testbench can poll this information anytime.
  • Registers to indicate the model state, bank state and initialization state
  • Initialization can be optionally skipped
  • Refresh can be optionally skipped
  • UVM Configuration: Users can configure the VIP agent using the UVM config class

Other Supported Features

Methodologies Unified Verification Methodology (UVM), OVM
Simulators IES, VCS, and MTI
Testbench Language Interfaces Verilog, VHDL, SystemVerilog, e, and SystemC
Trace Debug Yes