Home: IP Portfolio > Verification IP > Memory Models > DDR4 Memory Model

DDR4 Memory Model

Specification Support

DDR4 SDRAM Memory Model VIP supports the officially released JESD79-4 Rev 1.0 Specification and 3DS extensions. The specification is available here: www.jedec.org/sites/default/files/docs/JESD79-4.pdf

Key Features

Feature Name
Description
3DS Level Supports command decoding.
3DS Read/Write Supports 3DS Read/Write commands for 2H/4H/8H combinations
General DDR functionality and timing checks Precharge, Activate, Read, Write, Mode Register Write, Write levelling, ODT checks, Power Down, Self Refresh, Initializations and all related timing checks.
Reduced Pin count A16..A14 are multiplexed with ras, cas and webar pins and dedicated act pin for Activate command.
Data Width, Density

4, 8 and 16. 2Gb to 16Gb

Configurations New mode registers and associated settings.
Speed 1600, 1866, 2133
Bank Groups Modeling the concept and the timing associated with the back-to-back accesses to the same and difference bank group.
More Read Training Options More MPR registers organized as pages. More options of reading those registers and preamble training.
Reading of Mode Register Settings Some important setting of the more registers are shadowed into page-2 MPRs.
Data Mask and Data Bus Inversion Data on the bus can be inverted during both read and write to save power. Both Data Mask and Data Bus inversion features can be set through mode registers.
Per Dram Addressability Allows mode registers of each DRAM on the DIMM to be programmed independently.
CAL Mode Allows CSBAR to be asserted a few cycles before actual command details.
Write CRC CRC is checked for writes and error is flaged to the controller. CRC failures will let the write go through in the case that Data Mask is disabled and will block the writes in the case that Mask is enabled.
Parity Parity checking is off by default, but when enabled parity is checked for each command before execution and also detailed recovery in case of errors and reporting of logs through MPR Reads.
Control Gear Down Mode Allows the DRAM to operate in 2N mode.
New Read Output Delay tDQSCK jitters are officially defined in the spec and they drift per operating voltage and temperature. The VIP models this and allows the controller to configure the drift and skew.
Configurable Preamble Allows both 1CK and 2CK preambles to be selected for both read and writes.
Refresh options Normal mode refresh, Self refresh, Temperature controller self refresh, Low Power Array self refresh, and Fine-granularity refresh
Maximum Power Saving Mode

Preserving the mode registers setting, but data is lost.

RTT Complete modelling of all RTT values, RTT_NOM/RTT_Park/RTT_Wr with the internal register representing the value of RTT at a given point of time, based on the mode of operation.