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DDR4 LRDIMM Memory Model

Specification Support

DDR4 LRDIMM Memory Model VIP supports JEDEC DDR4 SDRAM Registered DIMM Design Specification(Rev 0.8) for RDIMM specificaion and follows JEDEC DDR4 Register - DDR4RCD01 - Rev 0.92 for the RCD specification.

Key Features

Feature Name
Description
Weak driver support Support for signal strength modeling. Users can use pull up or pull down on the inout pins and the model will be able to detect the signal strength and function like a real device.
DIMM Types DDR4 UDIMM, RDIMM, LRDIMM, DDR4 3DS, 3DS UDIMM, 3DS RDIMM and 3DS LRDIMM. 
New DIMM configuration support Raw Cards with CB bits mapped to middle of DQ/DQS buses

Configurable DIMM topology

Number of ranks and components with and the overall interconnect between DIMM, RCD and DRAM are configurable through SOMAs.
Flyby delays

Support for Flyby delay to specify wiring delays.

  • For UDIMMs, Flyby delays can be specified from DIMM connectors to each of the DRAMs individually.
  • For RDIMMs, Flyby delays can be specified from DIMM connectors to RCD for command and control pins, and from RCD Side A/B to each of the DRAMs individually.
  • For LRDIMMs, Flyby delays can be specified from DIMM connectors to RCD for command and control pins, and from RCD Side A/B to each of the DRAMs individually. 
    Additionally, for the inout pins, can specify the delay to and from DB to each DRAM inout ports.

Flyby delays can be changed on the fly using mmsomaset.

ECC checks bits Can optionally have a DRAM instanciation for checks bits.
Address Mirroring RDIMM will optionally mirror the address bits as mentioned in specification
DQ Maps Configurable DQ Maps to match one of the options mentioned in the spec
Init and Reset Models both with the Power Up Reset and Reset with Stable Power with all timing and pin validity checks
Core RCD forwarding logic DRAM MRS command handling, Inversion, mirroring, command latency, propagation delay, gating with parity checks, different cs modes, etc.
RCD Control Word Writes MRS7 interface for CWW and most of the control word settings
Parity
  • Supports optionally checking for even parity and incase of errors gating CWW and DRAM commands.
  • In case of errors gating supports CWW and DRAM commands.

  • Implements different recovery mechanisms defined in the specification.

CA training Support Clk to CA and ODT, CKE, CSBAR loop back modes