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DDR3 Memory Model

Specification Support

The DDR3 SDRAM Memory Model VIP supports the officially released JESD79-3 version of the DDR3 SDRAM specification. The model also supports the 3F version of the specification. The specification is available here: http://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf

Key Features

FEATURE NAME
DESCRIPTION

General DDR functionality and timing checks

Pre-charge, Activate, Read, Write, Mode Register Write, Write leveling, ODT checks, Power Down, Self Refresh, Initializations and all related timing checks.

State machine and timing checks

Implements and exposes DDR3SDRAM state machines natively to user's HVL (eg init state, bank state, model state) and performs specified timing checks.

DLL change and clock freq change

Model tracking state changes and assertion check and timing adjustments throughout the change sequence steps

Data Width, Density

500M - 8g density, x4 - x16 width

Configurations

All mode register fields

Speed

800, 1066, 1333, 1600 

Vendors

Micron, Elpida, Eorex, Hynix, Naya, Samsung, Windbond

Bank Groups

Modeling the concept and the timing associated with the back-to-back accesses to the same and difference bank group

Write-leveling

Leveling checks and feedback response including option for bit-to-bit skew

MPR Read Training

Multi-purpose register mode with pattern feedback for reads for read level training

Input Data Mask

Data on the bus for writes is appropriately masked according to mode enabled and data mask bus state

Drift Read Output Delay

tDQSCK jitter drift per operating voltage and temperature defined in the DDR4 spec can be enabled so the VIP models this according to configured drift and skew

Refresh options

Normal mode refresh, including refresh rate check, Self Refresh, Partial Array Self Refresh, Extended Temperature self refresh