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AVIP for PCIe 4.0

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for PCIe is a set of ready-made, highly configurable Verification IP for the PCI Express® (PCIe®) interface. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP platform.

The AVIP for PCIe can:

  • Behave as both Root Complex and End Point
  • Create and send PCIe transactions
  • Respond to PCIe transactions

Specification Support

All PCIe transactions are in accordance with the PCI Express 4.0 Specification.

Product Highlights

The following table lists the supported functionality of the AVIP for PCIe:

Functionality/Attributes

AVIP for PCIe 4.01

AVIP for PCIe CCIX 2
PCIe 1.0 Yes Yes
PCIe 2.0 Yes Yes
PCIe 3.0 Yes Yes
PCIe 4.0 Yes Yes
8/16-Bit PIPE Interface Yes Yes
32-Bit PIPE Interface Yes Yes
Multiple Virtual Channels Yes Yes
Address Translation Services (ATS) for UVM SystemVerilog Yes N/A
PASID Translation Yes N/A
ATS+PASID Translation Yes N/A
PRI Yes N/A
Serial Interface Yes No
Up to 16 Lanes Yes Yes
Power Management Yes Yes
Complete Set of Configuration/Status Registers Yes Yes
Logging Control and Transaction Logs in a Log File Yes Yes
2.5/5/8GT/s Speeds Yes Yes
16GT/s Speed Yes Yes
Backdoor Memory Access (read/write to own memory) Yes N/A
Stimulus Access to Received Transactions Using Callbacks Yes Yes
Events to Control Timing of Transactions
(reduces hardware/software syncs and gives control to stimulus)
Yes N/A
Single Root I/O Virtualization (SR-IOV) No No

Fully Supports the Following Transactions:

  • Memory Read and Write
  • Memory Read Lock
  • I/O Read and Write
  • Configuration Read and Write (Type 0 and Type 1)
  • Messages With Data and Without Data
Yes N/A

PCIe Complete ID Support for the Following Transactions:

  • Memory Read
  • I/O Read and Write
Yes N/A

Atomic Transactions Support for the Following:

  • 32-bit FETCH_ADD, SWAP and COMPARE_AND_SWAP
  • 64-bit FETCH_ADD, SWAP and COMPARE_AND_SWAP
  • 128-bit COMPARE_AND_SWAP
Yes N/A
10-Bit Tags Yes N/A
Zero-Length Transactions Yes N/A
Scaled Flow Control Yes N/A

1 The AVIP for PCIe 4.0 (16 Lane) is available at $AVIP_ROOT/cdn_pcie/hdl_16_gen4

2 The AVIP for PCIe CCIX is available at $AVIP_ROOT/cdn_pcie/hdl_ccix

Supported Interfaces

  • UVM SystemVerilog
  • C++

Supported Flows

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Root Complex End Point Hub/Switch
Full Stack Controller Only PHY Only

 

Usage Options

Simulation Acceleration HW/SW Co-Verification