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AVIP for PCI Express 5.0

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for PCIe is a set of ready-made, highly configurable Verification IP for the PCI Express® (PCIe®) interface. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium™ simulator, or in simulation acceleration with the Xcelium simulator and the Palladium platform.

The AVIP for PCIe can:

  • Behave as both Root Complex and End Point
  • Create and send PCIe transactions
  • Respond to PCIe transactions

Specification Support

All PCIe transactions are in accordance with the PCI Express 5.0 Specification Version 0.9.

Protocol Features

Supported interfaces:

  • C++

Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Key Verification Capabilities

The following table lists the supported functionality of the AVIP for PCIe:

Functionality/Attributes

AVIP for PCIe 5.0 1

PCIe 1.0 (2.5GT/s Speed)

Yes

PCIe 2.0 (5GT/s Speed)

Yes

PCIe 3.0 (8GT/s Speed)

Yes

PCIe 4.0 (16GT/s Speed)

Yes

PCIe 5.0 (32GT/s Speed)

Yes

8-bit PIPE Interface

No

16-bit PIPE Interface

Yes

32-bit PIPE Interface

Yes

Multiple Virtual Channels

Yes

Address Translation Services (ATS) for UVM SystemVerilog

No

PASID Translation

No

ATS+PASID Translation

No

PRI

No

Serial Interface

No

Up to 16 Lanes

Yes

Power Management

Yes

Complete Set of Configuration/Status Registers

Yes

Logging Control and Transaction Logs in a Log File

Yes

Backdoor Memory Access (read/write to own memory)

Yes

Stimulus Access to Received Transactions Using Callbacks

Yes

Events to Control Timing of Transactions 

(reduces hardware/software syncs and gives control to stimulus)

Yes

Single Root I/O Virtualization (SR-IOV)

Yes

Fully Supports the Following Transactions:

  • Memory Read and Write

  • Memory Read Lock

  • I/O Read and Write

  • Configuration Read and Write (Type 0 and Type 1)

  • Messages With Data and Without Data

Yes

PCIe Completer ID Support for the Following Transactions:

  • Memory Read

  • I/O Read and Write

Yes

Atomic Transactions Support for the Following:

  • 32-bit FETCH_ADDSWAP and COMPARE_AND_SWAP

  • 64-bit FETCH_ADDSWAP and COMPARE_AND_SWAP

  • 128-bit COMPARE_AND_SWAP

Yes

10-bit Tags

Yes

Zero-Length Transactions

Yes

Scaled Flow Control

Yes

Low Pin Count PIPE Interface

Yes

Support for SerDes Architecture

(with 10-bit, 20-bit, 40-bit, and 80-bit PIPE Interface)

Yes

 1 The AVIP for PCIe 5.0 (8 Lane) is available at$AVIP_ROOT/cdn_pcie/hdl_8_gen5

    The AVIP for PCIe 5.0 (16 Lane) is available at $AVIP_ROOT/cdn_pcie/hdl_16_gen5

 

Supported Design-Under-Test Configurations

Root Complex End Point Hub/Switch
Full Stack Controller Only PHY Only
 

Usage Options

Simulation Acceleration HW/SW Co-Verification

Documentation

  • PCIe Accelerated VIP User Guide

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