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AVIP for PCIe 2.0/3.0

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for PCIe is a set of ready-made, highly configurable Verification IP for the PCI Express® (PCIe®) interface. It enables tests to be run in a pure simulation environment, with the Cadence Incisive®Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP platform.

The AVIP for PCIe can:

  • Behave as both Root Complex and End Point
  • Create and send PCIe transactions
  • Respond to PCIe transactions

Specification Support

All PCIe transactions are in accordance with the PCI Express 3.0 Specification.

Product Highlights

The following table lists the supported functionality of the AVIP for PCIe:

FUNCTIONALITY/ATTRIBUTES

AVIP for PCIe 2.0/3.0
(8 Lane)1

AVIP for PCIe 2.0/3.0
(16 Lane)2

PCIe 1.0 Yes Yes
PCIe 2.0 Yes Yes
PCIe 3.0 Yes Yes
PCIe 4.0 No No
8/16-Bit PIPE Interface Yes Yes
32-Bit PIPE Interface No Yes
Multiple Virtual Channels No No
Address Translation Services (ATS) for UVM SystemVerilog No Yes
PASID Translation No No
ATS+PASID Translation No No
PRI No No
Serial Interface No Yes
Up to 16 Lanes 8 lanes only Yes
Power Management Yes Yes
Complete Set of Configuration/Status Registers Yes Yes
Logging Control and Transaction Logs in a Log File Yes Yes
2.5/5/8GT/s Speeds Yes Yes
16GT/s Speed No No
Backdoor Memory Access (read/write to own memory) Yes Yes
Stimulus Access to Received Transactions Using Callbacks Yes Yes
Events to Control Timing of Transactions 
(reduces hardware/software syncs and gives control to stimulus)
Yes Yes
Single Root I/O Virtualization (SR-IOV) No Yes

Fully Supports the Following Transactions:

  • Memory Read and Write
  • Memory Read Lock
  • I/O Read and Write
  • Configuration Read and Write (Type 0 and Type 1)
  • Messages With Data and Without Data
Yes Yes

PCIe Complete ID Support for the Following Transactions:

  • Memory Read
  • I/O Read and Write
No No

Atomic Transactions Support for the Following:

  • 32-bit FETCH_ADD, SWAP and COMPARE_AND_SWAP
  • 64-bit FETCH_ADD, SWAP and COMPARE_AND_SWAP
  • 128-bit COMPARE_AND_SWAP
No No
10-Bit Tags No No
Zero-Length Transactions No No
Scaled Flow Control No No

 1 The AVIP for PCIe 2.0/3.0 (8 Lane) is available at $AVIP_ROOT/cdn_pcie/hdl_8

 2 The AVIP for PCIe 2.0/3.0 (16 Lane) is available at $AVIP_ROOT/cdn_pcie/hdl_16

Supported interfaces:

  • UVM SystemVerilog
  • C++

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Root Complex End Point Hub/Switch
Full Stack Controller Only PHY Only

 

Usage Options

Simulation Acceleration HW/SW Co-Verification

 

User Feedback

“As Cadence promised, our validation environment now runs hundreds of times faster than with simulation. Accelerated VIP running on the Palladium XP increased my team’s productivity by 100%. It also enabled us to find bugs we were unable to reach using simulation.”

– Tony Gladvin George, Verification Engineer, Samsung