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AVIP for USB 3.1

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for USB 3.2 Gen 2 (USB 3.1) is a ready-made, highly configurable Verification IP for the USB interface. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium platform.

Specification Support

The AVIP for USB 3.2 Gen 2 is based on the following specification:

Product Highlights

  • 32-bit PIPE interface
  • 8-bit and 16-bit UTMI interface
  • Control, bulk, interrupt, and isochronous transactions are supported
  • Hi-Speed, SuperSpeed, SuperSpeedPlus data transfer in both Host and Device modes
  • Logs transactions in log file and logging control
  • Stimulus access to received transactions using callbacks
  • Configurable USB 2.0 and USB 3.2 Gen 2 timings using defines
  • Performs automatic link training when AVIP comes out of reset without any testbench activity
  • USB 3.2 Gen 1 On-The-Go (OTG) Revision 2.0, only HNP and SRP
  • Backward compatible with the AVIP for USB 2.0
  • Low-power capabilities
  • APIs for software reset and connect or disconnect
  • Audio Class Version 1.0 and 2.0 descriptor support
  • Bulk Only Transport (BOT)
  • USB Attached SCSI Protocol (UASP)

Supported interfaces:

  1. C++

Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification

Documentation

  • USB 3.2 Gen 2 Accelerated VIP User Guide

Related Products

  • Palladium Verification Computing Platform