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AVIP for USB 2.0

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for USB 2.0 is a ready-made, highly configurable Verification IP for the USB interface. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium platform.

Specification Support

The AVIP for USB 2.0 is based on the USB 2.0 specification (http://www.usb.org/developers/docs/).

Product Highlights

The AVIP for USB 2.0 supports the following features:

  • 16-bit UTMI (UTMI 1.05 and UTMI+ Level 1) interface

  • The signal-level interface is connected via a UTMI+ interface to the DUT

  • Control, bulk, interrupt, and isochronous transfers

  • Full-Speed, Hi-Speed data transfer in both Host and Device modes
  • Configurable for up to 15 IN and 15 OUT endpoints and one Control endpoint
  • Logs transactions in a log file and logging control

  • Stimulus access to received transactions using callbacks

  • Low power management

  • Device Firmware Upgrade (DFU) Revision 1.1 capability (USB 2.0 AVIP Host only)
  • USB On-The-Go (OTG) Revision 1.3
  • USB 2.0 Host and USB 2.0 Device
  • Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) of USB OTG Revision 1.3
  • USB Device Class Definition for Audio Devices Revision 2.0 capability (AVIP for USB 2.0 Host only)

  • Supports Interface Association Descriptor as per ECN for USB Revision 2.0
  • Supports Ease-Of-Use (EOU) scripts

Supported interfaces:

  • The AVIP for USB 2.0 supports the following testbench interfaces:

    • C++
    • UVM SystemVerilog

Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification