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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for SimCard is a ready-made, highly configurable Verification IP for the SimCard protocol. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium platform.

Specification Support

The AVIP for SimCard is based on the SIM BFM Requirement Specification, Version 0.7 –14 August 2012.

Product Highlights

  • Synthesizable Bus Functional Model (BFM) compliant with  ISO/IES 7816-3 standard that supports Card mode only (Slave)
  • Internal registers for configuration
  • Configurable T0/T1 protocol parameters
  • Support direct/inverse mode data convention
  • Supports complete activation/deactivation sequence
  • Integrated card state monitor register
  • Error injection for sent packets and error detection for received packets

Supported interfaces:

  • C++
  • UVM SystemVerilog

Supported flows: 

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow


Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification