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AVIP for SATA 1.5/3/6G

The Cadence® Accelerated VIP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for SATA is a ready-made, highly configurable Verification IP for the SATA interface. It acts as a SATA device that is synthesized into the Palladium platform. It uses Palladium memory in place of the rotating platter of a SATA drive.

It enables tests to be run in:

  • A pure simulation environment, with the Cadence Xcelium simulator

  • Simulation Acceleration with the Xcelium simulator and the Palladium platform

  • In-Circuit Emulation with the Palladium platform

Specification Support

The AVIP for SATA is based on the Serial ATA Specification 3.0 and the ATA Command Set specification, ATA8 version.

Product Highlights

  • Supports the PIPE interface in the AVIP for SATA Device as a Beta feature

  • Supports simulator Save/Restore in the AVIP for SATA Device

  • Supports the SATA Device for use with simulation acceleration and In-Circuit Emulation. When used with In-Circuit Emulation, it can be used in both STB and LA modes.

  • The memory inside the SATA Device can be read and written using the Palladium MARG interface, or by using the xeDebug memory commands. This enables a disk image to be loaded and unloaded into the SATA Device as part of a test.

  • Supports SATA Device Disk for the following classes of ATA commands (ATA-8):
    • PIO Read and Write
    • DMA Read and Write
    • Non-Data Commands
    • Queued DMA Commands

Currently, only the SATA Device and Disk Drive Model are supported. Contact Cadence if you have a request for a SATA Host Bus Adapter (HBA).

  • Supports the Serial-ATA PHY Interface Specification (SAPIS) drafted by Intel Corp
  • Supports 10-bit and 20-bit data interfaces
  • Supports serial interface
  • Supports Gen 1, Gen 2, and Gen 3 speeds
Supported interfaces:
  • Embedded
  • UVM SystemVerilog
  • C++

Supported flows:

PXP Legacy ICE—xeCompile
PXP Legacy ICE—vavlog, vaelab
Yes Yes, for embedded Yes, for embedded Yes, for embedded


 Supported Design-Under-Test Configurations

Host Device Port Multiplier
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification