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AVIP for Keypad

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for Keypad is a ready-made, highly configurable Verification IP for the Keypad protocol. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with Xcelium simulator and the Palladium platform.

Specification Support

The AVIP for Keypad is based on the KEYPAD BFM Requirement Specification, Version 0.4 –19 July 2012.

Product Highlights

  • Synthesizable Bus Functional Model (BFM) supports 8x8 KEYPAD matrix

Supported Interfaces

  • C++
  • UVM SystemVerilog

Supported Flows

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow


Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Keypad Options

Simulation Acceleration HW/SW Co-Verification