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AVIP for I2C

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for I2C is a ready-made, highly configurable Verification IP for the I2C protocol. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium platform.

Specification Support

The AVIP for I2C is based on the following specifications:

  • I2C-bus specification and user manual, Rev. 03 — 19 June 2007

Product Highlights

The AVIP for I2C supports the following:

  • Synthesizable Bus Functional Model (BFM) compliant with I2C standard
  • Internal registers for configuration
  • Further I2C standard [4]-compliant features:
    • Configurable to both I2C Master or I2C Slave
    • BFM can operate as receiver or transmitter in both Master or Slave mode
    • Fully configurable I2C packets:
      • Standard-mode, Fast-mode, Fast-mode Plus, High-speed mode for both Master and Slave mode
      • START, STOP, REPEATED START generation, ACKNOWLEDGE, NOT ACKNOWLEDGE generation/detection in Master mode
      • START, STOP, REPEATED START detection, ACKNOWLEDGE, NOT ACKNOWLEDGE generation/detection in Slave mode
      • Multi-Master topology support
        • Synchronization
        • Arbitration
        • Configurable Master mode
      • General call support in both Master and Slave mode
      • 7-bit and 10-bit addressing is supported in both Master and Slave mode
      • START byte detection in Slave mode
    • Master BFM supports sending software reset via I2C
    • Slave BFM can issue clock stretching
    • Master BFM can manage clock stretching

Protocol Features

Supported interfaces:

  • C++
  • UVM SystemVerilog

Supported flows: 

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification

Training