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AVIP for USB 3.0

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for USB 3.0 is a ready-made, highly configurable Verification IP for the USB interface. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP platform.

The AVIP for USB 3.0 is complementary to Cadence Simulation VIP for USB 3.0, and enables you to easily move from simulation to simulation acceleration.

Specification Support

The AVIP for USB 3.0 is based on the USB 3.0 specification (http://www.usb.org/developers/docs/).

Product Highlights

  • 8-bit, 16-bit, and 32-bit PIPE interface
  • Serial interface
  • The signal-level interface is connected via a Serial or PIPE interface to the DUT
  • Control, bulk, interrupt, and isochronous transactions are supported
  • Logs transactions in log file and logging control
  • Stimulus access to received transactions using callbacks
  • Power management
  • Performs automatic link training when AVIP comes out of reset without any testbench activity
  • Audio Class Version 1.0 and 2.0 descriptor support
  • Bulk Only Transport (BOT)
  • USB Attached SCSI Protocol (UASP)
  • Device firmware upgrade (DFU)
  • Enumeration bypass using APIs
  • USB 3.0 On-The-Go (OTG)
  • Backward compatible with the AVIP for USB 2.0
  • Low power capabilities
  • APIs for software reset and connect/disconnect

Supported interfaces:

  • UVM SystemVerilog
  • C++
    • XHCI C++

    • USB Transaction C++

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification

Training