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AVIP for I2S

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for I2S is a ready-made, highly configurable Verification IP for the I2S protocol. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with Incisive Enterprise Simulator and the Palladium XP platform.

Specification Support

The AVIP for I2S is based on the following specifications:

  • I2S bus specification, Philips Semiconductors - 5 June 1996

Product Highlights

  • Synthesizable Bus Functional Model (BFM) compliant with I2S standard
  • Internal registers for configuration
  • Configurable to I2S Transmitter or I2S Receiver
  • Configurable to I2S Master or I2S Slave
  • TDM feature in the C++ interface, with configurable number of channels

Supported Interfaces

  • C++
  • UVM SystemVerilog

Supported Flows

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification