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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

Specification Support

Product Highlights

  • Supports generating CCIX transactions from multiple CCIX agents
  • CCIX transactions are converted to PCI Express® (PCIe®) and sent over a PCIe Link; CCIX can be configured to support both vendor-defined messages (Compliant Header), and optimized messages
  • Supports both RNF and HNF agent types
  • Supports an internal cache for HNF agents, with an option to automatically respond from the cache
  • Supports an internal memory for RNF agents, with an option to automatically respond from the memory
  • All CCIX transaction types (except for the ones listed in the Limitations of the CCIX AVIP)
  • Automatic credit handling
  • Multiple RNF/HNF agents on top of a single PCIe link

Supported interfaces:

  • UVM SystemVerilog
Supported flows:
  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow.

NOTE: Verilog modules must be compiled using BCU Compiler and not IXE questQel. In addition, CTB is a mandatory flag for the BCU and irun phases.

 Supported Design-Under-Test Configurations

RA (Request Agent) HA (Home Agent) Hub/Switch
Full Stack Controller Only PHY Only



  • CCIX Accelerated VIP User Guide

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