Home: IP Portfolio > Verification IP > Accelerated VIP > AVIP for MIPI DSI-2

AVIP for MIPI DSI-2

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for DSI-2 is a ready-made, highly configurable Verification IP for the MIPI® Display Serial Interface (DSI-2sm) protocol. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP platform.

Specification Support

The AVIP for DSI is based on the following specifications:

  •  MIPI Alliance Specification for Display Serial Interface 2 (DSI-2), Version 1.1 – 02 May 2018
  •  MIPI Alliance Specification for D-PHYsm, Version 2.0, MIPI Alliance, Inc. – In Press

Product Highlights

  • Configurable to DSI Peripheral or DSI Host
  • Supports all lane configurations in D-PHY with Parallel Interface (PPI) for 8,16, and 32 bits
  • Multi virtual-channel support in Peripheral mode
  • Fully configurable DSI packets in Host mode
  • Embedded digital model of D-PHY
  • Bus turnaround support in both Host and Peripheral mode
  • Supports the ACK and TE triggers over D-PHY
    • Supports D-PHY Parallel Interface (PPI) when using the C++ and UVM SystemVerilog interfaces
    • Supports D-PHY Serial interface when using the C++ and UVM SystemVerilog interfaces
  • Supports the SimAccel consistency classes to enable a single set of classes and API which supports both the VIP and AVIP
  • Error injection in Host mode and error detection in Peripheral mode—supporting both DSI-level (ECC, CRC) and low-level protocol error detection

Supported Interfaces

  • C++
  • UVM SystemVerilog

Supported Flows

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Host Peripheral Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification