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AVIP for MIPI DSI

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for DSI is a ready-made, highly configurable Verification IP for the MIPI® Display Serial Interface (DSIsm) protocol. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium platform.

Specification Support

The AVIP for DSI is based on the following specifications:

  • MIPI Alliance Specification for C-PHYsm, Version 1.2, MIPI Alliance, Inc. – 26 November 2016
  • MIPI Alliance Specification for Display Serial Interface (DSI), Version 1.3.1 – 31 August 2015
  • MIPI Alliance Specification for D-PHYsm, Version 1.2, MIPI Alliance, Inc. – 01 August 2014

Product Highlights

  • Supports the C-PHY 1.2 Serial interface HS transmission on the device side, including multi-packet frames mode
  • Supports the C-PHY 1.2 PPI interface HS transmission on the device side, including multi-packet frames mode
  • Configurable to DSI Peripheral or DSI Host
  • Supports all lane configurations in D-PHY with Parallel Interface (PPI) for 8 bits
  • Multi virtual-channel support in Peripheral mode
  • Fully configurable DSI packets in Host mode
  • Embedded digital model of D-PHY
  • Bus turnaround support in both Host and Peripheral mode
  • Supports the ACK and TE triggers over D-PHY
    • Supports D-PHY Parallel Interface (PPI) when using the C++ and UVM SystemVerilog interfaces
    • Supports D-PHY Serial interface when using the C++ and UVM SystemVerilog interfaces
  • Supports the SimAccel consistency classes to enable a single set of classes and API which supports both the VIP and AVIP
  • Additional RGB 8:8:8 interface that can be connected directly to Display module (supports up to four lanes, as well as all transmission modes: "burst," "non-burst sync pulse," and "non-burst sync events")
  • Error injection in Host mode and error detection in Peripheral mode—supporting both DSI-level (ECC, CRC) and low-level protocol error detection

Supported Interfaces

  • C++
  • UVM SystemVerilog

Supported Flows

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Host Peripheral Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification