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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for MIPI DBI is a ready-made, highly configurable Verification IP for the MIPI® Display Bus Interface (DBIsm) protocol. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with Incisive Enterprise Simulator and the Palladium XP platform.

Specification Support

The AVIP for DBI is based on the following specifications:

  • MIPI Alliance Standard for Display Bus Interface, Version 2.0 – 16 November 2005
  • MIPI Alliance Standard for Display Command Set, Version 2.0 – 16 November 2005

Product Highlights

  • Configurable to DBI Peripheral or DBI Host
  • Synthesizable Bus Functional Model (BFM) for DBI device
  • Internal registers for configuration
  • Type-B and Type-C interface support
  • Supports the whole DCS command set
  • Configurable data width to 8,9,16,18 bits in Type-B mode
  • Configurable length of read/write cycle (each byte is either 8, 9, or 16 write cycles) in Type-C mode
  • Support for Break and Pause sequences in Type-C mode

Supported Interfaces

  • C++
  • UVM SystemVerilog

Supported Flows

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification