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AVIP for MIPI CSI-2

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for CSI-2 is a ready-made, highly configurable Verification IP for the MIPI® Camera Serial Interface 2 (CSI-2sm) protocol. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with Incisive Enterprise Simulator and the Palladium XP platform.

Specification Support

The AVIP for CSI-2 is based on the following specifications:

  • MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2sm) Version 2.0 – 7 December 2016

Product Highlights

  • Supports the embedded CSI-2 device interface for the D-PHY configurations
  • Configurable to CSI-2 Peripheral or CSI-2 Host
  • Fully configurable CSI-2 packets in Peripheral mode
  • Supports all lane configurations in D-PHYsm with serial interface
  • Supports all lane configurations in C-PHYsm with serial interface
  • Supports the C-PHYsm serial interface for 16 and 32 bits
  • Supports all lane configurations in D-PHYsm with Parallel Interface (PPI) for 8, 16, and 32 bits
  • Supports all lane configurations in C-PHYsm with Parallel Interface (PPI) for 16 and 32 bits
  • Fully supports enabling all of the RX and TX Virtual Channel fields, for the C++ and UVM SystemVerilog interfaces. In C-PHY, supports up to 32 channels. In D-PHY, supports up to 16 channels when using the Specification for Camera Serial Interface 2 (CSI-2) Version 2.0 or a higher release
  • Supports triggers for Serial interface and PPI interface for all lanes configurations, for the C++ and UVM SystemVerilog interfaces
  • Internal registers for configuration
  • Embedded digital model of D-PHYsm and C-PHYsm
  • Error injection in Peripheral mode and error detection in Host mode – supporting CSI-2 level (ECC, CRC) protocol error detection

Supported Interfaces

  • C++
  • UVM SystemVerilog

Supported Flows

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Host Peripheral Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification