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AVIP for Ethernet USXGMII

The Cadence® Accelerated Verification IP (AVIP) for Ethernet USXGMII enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for Ethernet is a set of ready-made, highly configurable Verification IP for Ethernet USXGMII. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for Ethernet USXGMII is a complementary product to the Cadence VIP for Ethernet, and enables simulation acceleration and virtual emulation with the C++ or UVM SystemVerilog environment, for subsystem- and system-level verification.

Specification Support

The AVIP for Ethernet is compliant with the IEEE 802.3 standard.

Product Highlights

  • Supports C++ and UVM SystemVerilog user interfaces
  • Compatible with a multi-AVIP environment

USXGMII Features

  • Supports the following configurations:

    • 10G_SXGMII

    • 10G_QXGMII

    • 5G_DXGMII

    • 2_5G_SXGMII

    • 5G_SXGMII

    • 20G_OXGMII

    • 20G_QXGMII

    • 20G_DXGMII

  • Supports all port speeds as per the specification: 10G/5G/2.5G/1G/100M/10M

  • Supports 32-bit interface width

  • Supports Auto Negotiation (AN)

  • Supports the non-FEC mode

Supported interfaces:

Currently, the AVIP for Ethernet supports the following:

User/TB Interface
Interface 
Speed Mode
Interface Width

C++

USXGMII Multispeed 32-bit
UVM SystemVerilog USXGMII Multispeed 32-bit

Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Documentation

  • Ethernet Accelerated VIP User Guide

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