The AVIP library for Ethernet is a set of ready-made, highly configurable Verification IP for Ethernet Multiplexed PCS

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AVIP for Ethernet Multiplexed PCS

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for Ethernet is a set of ready-made, highly configurable Verification IP for Ethernet Multiplexed PCS. It enables tests to be run in a pure simulation environment, with the Cadence Incisive®Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP Verification Computing Platform.

The AVIP for Ethernet is an extension of the Cadence VIP for Ethernet, and enables you to either move from simulation with the VIP for Ethernet to—or create a new C++ environment for—simulation acceleration.

Specification Support

The AVIP for Ethernet is compliant with the IEEE 802.3 standard.

Product Highlights

  • Supports C++ user interface
  • Is compatible with a multi-AVIP environment
  • Capability to switch the speed mode without recompilation of the design

For supported features, see the following:

Supported interfaces:

Currently, the AVIP for Ethernet supports the following:

User/TB InterfaceInterface Speed ModeInterface Width

C++

Multiplexed PCS Multispeed

40-bit (4 lanes)

80-bit (8 lanes)

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Training

Documentation

  • Ethernet Accelerated VIP User Guide

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