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AVIP for Ethernet 40G/100G

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for Ethernet is a set of ready-made, highly configurable Verification IP for Ethernet 40G/100G. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP Verification Computing Platform.

The AVIP for Ethernet is an extension of the Cadence VIP for Ethernet, and enables you to either move from simulation with the VIP for Ethernet to—or create a new C++ environment for—simulation acceleration.

Specification Support

The AVIP for Ethernet is compliant with the IEEE 802.3 standard.

Product Highlights

  • Is compliant with IEEE 802.3 for MAC and PCS

  • Is highly configurable via register and the control interface

  • Implements 100% of the protocol as synthesizable RTL

  • Supports C/C++/SystemC® and UVM SV user interfaces

  • Is compatible with a multi-AVIP environment

40G and 100G MAC Features

  • XLGMII interface for Ethernet 40G

  • CGMII interface for Ethernet 100G

  • 64/128/192-bit configurable XLGMII/CGMII to the Physical layer

  • Full-duplex operation

  • Automatic preamble, pad, and CRC generation on transmitted frames

  • Physical layer management through the MDIO interface

  • Jumbo frames of up to 9K bytes

  • Support for pause frames

  • Support for IEEE 802.1Q VLAN tags

  • Support for IEEE 802.1Qbb priority-based flow control frames

  • Configurable inter-packet gaps (IPGs)

40GBASE-R and 100GBASE-R Features

  • 16-bit, 32-bit, or 40-bit, 4-lane SerDes interfaces for 40G

  • 16-bit or 32-bit 10-lane SerDes interfaces for 100G

  • 40-bit 4-lane SerDes interfaces for 100G

  • 80-bit 4-lane SerDes interfaces for 100G

  • 64/66 block encoding and decoding

  • Data scrambler on transmit path and de-scrambler on receive path

  • Block synchronization

  • Alignment marker insertion and deletion

  • Lane-to-lane deskew

  • Lane re-ordering

100GBASE-R(RS-FEC) Features

  • 40-bit 4-lanes SerDes interfaces for 100G PCS

  • 64b/66b encoding and decoding

  • 256/257b transcoding and reverse transcoding

  • Data scrambler on transmit path and de-scrambler on receive path

  • Block synchronization

  • Alignment marker insertion and deletion

  • Lane-to-lane deskew

  • Lane re-ordering

  • RS (544,514)encoding

Other Supported Features

The AVIP for Ethernet supports all types of Ethernet transactions, including:

  • Ethernet v2 frames

  • Ethernet IEEE 802.3 frames

  • Pause frames

  • Priority pause frames

  • Jumbo frames

  • VLAN tagged frames

Supported interfaces:

Currently, the AVIP for Ethernet supports the following:

User/TB InterfaceInterface Speed ModeInterface Width
C++ XLGMII   40G   64-bit
128-bit
192-bit
40GBASE-R 40G 16-bit (4 lanes)
32-bit (4 lanes)
40-bit (4 lanes)
CGMII 100G  64-bit
128-bit
192-bit
100GBASE-R 100G 16-bit (10 lanes)
20-bit (10 lanes)
32-bit (10 lanes)
100GBASE-R (RS-FEC) 100G 40-bit (4 lanes)
UVM SystemVerilog         XLGMII   40G 64-bit
128-bit
192-bit
40GBASE-R 40G 16-bit (4 lanes)
32-bit (4 lanes)
CGMII 100G 64-bit
128-bit
192-bit
100GBASE-R 100G 16-bit (10 lanes)
20-bit (10 lanes)
32-bit (10 lanes)
40-bit (4 lanes)
80-bit (4 lanes)

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow


Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification