Home: IP Portfolio > Verification IP > Accelerated VIP > AVIP for Ethernet 25G/50G

AVIP for Ethernet 25G/50G

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for Ethernet is a set of ready-made, highly configurable Verification IP for Ethernet 25G/50G. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP platform.

The AVIP for Ethernet 25G/50G is a complementary product to the Cadence VIP for Ethernet, and enables simulation acceleration and virtual emulation with the C++ or UVM SystemVerilog environment, for subsystem- and system-level verification.

Product Highlights

  • Supports C++ and UVM SystemVerilog user interfaces
  • Is compatible with a multi-AVIP environment

XXVGMII MAC (25G MAC-PHY Interface) Features
  • Full duplex operation
  • Dual-edge 32-bit interface to the physical layer
  • Automatic preamble, pad, and CRC generation on transmitted frames
  • Promiscuous mode where all valid received frames are forwarded
  • Physical layer management through the MDIO interface
  • Jumbo frames of up to 9K bytes
  • Support for Pause frames
  • Support for IEEE 802.1Q VLAN tags
  • Support for IEEE 802.1Qbb priority-based flow control frames
  • Configurable inter-packet gaps (IPGs)
25G PHY (PCS) Features
  • 40-bit SerDes interface for 25G PCS
  • 64b/66b encoding and decoding with support for all reserved codes and signal ordered set
  • Data scrambler on transmit path and de-scrambler on receive path
  • Block synchronization
LGMII MAC (50G MAC-PHY Interface) Features
  • Full duplex operation
  • Single-edge 64-bit interface to the physical layer
  • Automatic preamble, pad, and CRC generation on transmitted frames
  • Promiscuous mode where all valid received frames are forwarded
  • Physical layer management through the MDIO interface
  • Jumbo frames of up to 9K bytes
  • Support for Pause frames
  • Support for IEEE 802.1Q VLAN tags
  • Support for IEEE 802.1Qbb priority-based flow control frames
  • Configurable inter-packet gaps (IPGs)
50G PHY (PCS) Features
  • 40-bit 2-lanes SerDes interfaces for 50G PCS
  • 64b/66b encoding and decoding
  • Data scrambler on transmit path and de-scrambler on receive path
  • Block synchronization
  • Alignment marker insertion and deletion
  • Lane-to-lane deskew
  • Lane re-ordering

50G PCS (RS-FEC) Features

  • 40-bit 2-lanes SerDes interfaces for 50G PCS
  • 64b/66b encoding and decoding
  • 256/257b transcoding and reverse transcoding
  • Data scrambler on transmit path and de-scrambler on receive path
  • Block synchronization
  • Alignment marker insertion and deletion
  • Lane-to-lane deskew
  • Lane re-ordering
  • RS (544, 514) encoding

Other Supported Features
The AVIP for Ethernet supports all types of Ethernet transactions, including:

  • Ethernet v2 frames
  • Ethernet IEEE 802.3 frames
  • Pause frames
  • Priority pause frames
  • Jumbo frames
  • VLAN tagged frames

Supported Interfaces

Currently, the AVIP for Ethernet supports the following:

User/TB InterfaceInterface Speed ModeInterface Width
C++         XXVGMII 25G 32-bit
25G-PCS 25G 40-bit
LGMII 50G 64-bit
50G-PCS 50G 40-bit (2 lanes)
50G-PCS (RS-FEC) 50G 40-bit (2 lanes)
UVM SystemVerilog         XXVGMII 25G 32-bit
25G-PCS 25G 40-bit
LGMII 50G 64-bit
50G-PCS 50G 40-bit (2 lanes)

 Supported Flows

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification