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AVIP for Ethernet 200G/400G

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for Ethernet is a set of ready-made, highly configurable Verification IP for Ethernet 200G/400G. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP Verification Computing Platform.

The AVIP for Ethernet 200G/400G is a complementary product to the Cadence VIP for Ethernet, and enables simulation acceleration and virtual emulation with the C++ environment, for subsystem- and system-level verification.

Specification Support

The AVIP for Ethernet is compliant with the IEEE 802.3 standard.

Product Highlights

  • Supports C++ user interface
  • Is compatible with a multi-AVIP environment

200G/400G MAC (200G/400G MAC-PHY Interface) Features

  • Full duplex operation
  • Single-edge 64-bit interface to the physical layer
  • Automatic preamble, pad, and CRC generation on transmitted frames
  • Promiscuous mode where all valid received frames are forwarded
  • Jumbo frames of up to 16K bytes
  • Support for pause frames (only transmission)
  • Support for IEEE 802.1Q VLAN tags
  • Support for IEEE 802.1Qbb priority-based flow control frames (only transmission)
  • Configurable inter-packet gaps (IPGs)

200G/400G PHY Features

  • 40-bit 16-lanes SerDes interfaces for 400G PCS
  • 80-bit 8-lanes SerDes interfaces for 400G PCS
  • 40-bit 8-lanes SerDes interfaces for 200G PCS
  • 80-bit 16-lanes SerDes interfaces for 200G PCS
  • 64b/66b encoding and decoding
  • 256/257b transcoding and reverse transcoding
  • Data scrambler on transmit path and de-scrambler on receive path
  • Block synchronization
  • Alignment marker insertion and deletion
  • Lane-to-lane deskew
  • Lane re-ordering
  • RS (544,514) encoding
  • PAM4 encoding

Supported interfaces:

Currently, the AVIP for Ethernet supports the following:

User/TB InterfaceInterface Speed ModeInterface Width

C++

CCGMII 200G 256-bit
200GBASE-R
200G

40-bit (8 lanes)

80-bit (4 lanes)
CDGMII 400G 256-bit
400GBASE-R 400G

40-bit (16 lanes)

80-bit (8 lanes)

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow