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AVIP for Ethernet 1G/10G

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for Ethernet is a set of ready-made, highly configurable Verification IP for Ethernet. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for Ethernet 1G/10G is a complementary product to the Cadence VIP for Ethernet, and enables simulation acceleration and virtual emulation with the C++, TLM2, or UVM SystemVerilog environment, for subsystem- and system-level verification.

Specification Support

The AVIP for Ethernet is compliant with the IEEE Standard 802.3.

Product Highlights

  • Is compliant with IEEE 802.3 for MAC and PCS

  • Is highly configurable via register and the control interface

  • Implements 100% of the protocol as synthesizable RTL

  • Supports C/C++/SystemC®, TLM 2.0, and UVM SystemVerilog user interfaces

  • Is compatible with a multi-AVIP environment

1G MAC (1G/10M/100M) Features

  • 10, 100, and 1000 Mbps operation

  • Full duplex operation

  • Support for RMII interface

  • Support for RGMII interface

  • Support for SGMII interface to an external PHY design

  • Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames

  • Physical layer management through the Management Data Input/Ouput (MDIO) interface

  • MDIO slave interface decoupled with the other Ethernet functionality

  • Jumbo frames up to 16383 bytes

  • Support for pause frames

  • Support for IEEE 802.1Q VLAN tags

  • Support for IEEE 802.1Qbb priority-based flow control frames

  • Configurable inter-packet gaps (IPGs)

  • Support for low-power idles (LPIs)

1G PCS 10-Bit Interface (TBI) Features

  • Connects to a 1Gbit SerDes using a 10-bit PCS interface

  • 8b/10b code encoding and decoding

  • Supports autonegotiation (IEEE clause 37)

  • Support for LPIs

Multiplexed 1G Features

  • 10, 100, and 1000 Mbps operation
  • Full duplex operation
  • Support for RMII interface
  • Support for RGMII interface
  • Support for SGMII interface to an external PHY design
  • Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames
  • Physical layer management through the Management Data Input/Ouput (MDIO) interface
  • MDIO slave interface decoupled with the other Ethernet functionality
  • Jumbo frames up to 16383 bytes
  • Support for pause frames
  • Support for IEEE 802.1Q VLAN tags
  • Support for IEEE 802.1Qbb priority-based flow control frames
  • Configurable inter-packet gaps (IPGs)
  • Support for low-power idles (LPIs)
  • Connects to a 1Gbit SerDes using a 10-bit PCS interface
  • 8b/10b code encoding and decoding
  • Supports autonegotiation (IEEE clause 37)
  • Support for LPIs

10G MAC Features

  • Full duplex operation

  • Dual-edge 32-bit and single-edge 64-bit XGMII interface to the physical layer

  • Automatic preamble, pad, and CRC generation on transmitted frames

  • Promiscuous mode where all valid received frames are forwarded

  • Physical layer management through the Management Data Input/Ouput (MDIO) interface

  • MDIO slave interface decoupled with the other Ethernet functionality

  • Jumbo frames of up to 9K bytes

  • Support for pause frames

  • Support for IEEE 802.1Q VLAN tags

  • Support for IEEE 802.1Qbb priority-based flow control frames

  • Configurable inter-packet gaps (IPGs)

  • Supports Interspersing Express Traffic

10G PHY (PCS) Features

  • Connects to a 10Gbit SerDes using a 16-bit, 32-bit, and 64-bit PCS interface

  • 64/66B encoding and decoding with support for all reserved codes and signal ordered set

  • Data scrambler on transmit path and de-scrambler on receive path

  • Optional support for Forward Error Correction (FEC)

Other Supported Features

The AVIP for Ethernet supports all types of Ethernet transactions, including:

  • Ethernet v2 frames

  • Ethernet IEEE 802.3 frames

  • Pause frames

  • Priority pause frames

  • Jumbo frames

  • VLAN tagged frames

The AVIP for Ethernet supports following mPacket transactions for the 10G speed mode:

  • Express packet
  • Complete preemptable packet
  • Initial fragment of a preemptable packet
  • Continuation fragment of a preemptable packet
  • End fragment of a preemptable packet

Supported interfaces:

Currently, the AVIP for Ethernet supports the following:

           

User/TB Interface

Interface 

Speed Mode

Interface Width

C++

MII

10M

4-bit

100M

4-bit

GMII

1G

8-bit

RMII

10M

2-bit

100M

2-bit

RGMII

10M

4-bit

100M

4-bit

1G

4-bit

SGMII

10M

1-bit or 10-bit

100M

1-bit or 10-bit

1G

1-bit or 10-bit

TBI

1G

10-bit

Multiplexed 1G

Multispeed

Multi-width

XGMII

10G

32-bit

64-bit

XSBI

10G

16-bit

32-bit

64-bit

TLM2 MII 10M 4-bit
100M 4-bit
GMII 1G 8-bit
RGMII 1G 4-bit
XGMII 10G 32-bit
64-bit
XSBI  10G  16-bit
32-bit
64-bit
UVM SystemVerilog                     MII 10M 4-bit
  100M 4-bit
GMII 1G 8-bit
RGMII 10M 4-bit
  100M 4-bit
  1G 4-bit
TBI 1G 10-bit
XGMII 10G 32-bit
XSBI 10G 16-bit
32-bit
64-bit

 Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification

Documentation

  • Ethernet Accelerated VIP User Guide

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