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AVIP for HDMI 2.0

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for HDMI is a set of ready-made, highly configurable Verification IP for the HDMI interface. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP Verification Computing Platform.

The AVIP for HDMI is an extension of the Cadence VIP for HDMI, and enables migration from simulation with the VIP for HDMI to simulation acceleration.

Specification Support

The AVIP library for HDMI is based on the HDMI Specification Version 2.0 (http://hdmiforum.org/). The AVIP for HDMI 2.0 is backward compatible with the AVIP for HDMI 1.4.

Product Highlights

Supported HDMI 2.0 features: 

  • All CEA-861-1 Video Information Codes
  • Status and Control Data Channel (SCDC) Registers
  • Scrambling for EMI
  • YCbCr 4:2:0 based pixel encoding 
  • New Data Island Formats
  • New E-EDID Data Blocks

 

Supported interfaces:

  • C++

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow


Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification

Training