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AVIP for HDMI 1.3/1.4

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for HDMI is a set of ready-made, highly Verification IP for the HDMI interface, and has full support for advanced 3D and Extended Resolution (4Kx2K) frames supported by the HDMI 1.4 specification. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for HDMI 1.3/1.4 is a complementary product to the Cadence VIP for HDMI, and enables simulation acceleration and virtual emulation with the C++ or UVM SystemVerilog environment, for subsystem- and system-level verification.

Specification Support

The AVIP library for HDMI is based on HDMI Specification Version 1.4b (http://www.hdmi.org/).

Product Highlights

Supported HDMI 1.4b features:

  • All Extended Resolution frames

  • All HDMI 3D frame format types, including:

    • Frame packing (for both Progressive and Interlaced frame types)
    • Side-by-side—Half
    • Top and bottom
    • Field alternative
    • Line alternative
    • Side-by-side—Full
    • L+Depth
    • L+Depth+Graphics+GraphicsDepth 

Supported HDMI 1.3a features:

  • All types of Data Islands

  • All video frame types

  • All VIC values listed in CEA-861-E

  • Support for full 32KB E-EDID address space

  • CEC channel

  • HDCP authentication/key exchange over I2C

Supported interfaces:

  • UVM SystemVerilog (HDMI 1.4 only)
  • C++

Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification