Home: IP Portfolio > Verification IP > Accelerated VIP > AVIP for DisplayPort

AVIP for DisplayPort

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for DisplayPort enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for DisplayPort enables simulation acceleration and virtual emulation with the C++ environment, for subsystem- and system-level verification.

Specification Support

The AVIP for DisplayPort is based on the following specification:

  • Video Electronics Standards Association (VESA) DisplayPort (DP) Standard, Version 1.4

Product Highlights

  • Full implementation for AUX RX or TX path with 1-bit serial interface

  • HPD assertion or de-assertion from Sink.

  • Full SST implementation with Enhanced Framing for 4-Lane Traffic with the user-defined SDP-Parity

  • Support for 8/16/32 and 10/20/40 bits per lane bit width

  • Automatic Full Link Training Sequence with support for re-training

  • Automatic Calculation for MSA based on Frame Calculation

  • Automatic insertion or scheduling for the Frame

  • Support for Fill Insertion based on the Link Rate

  • The Frame parameters are strictly decoded from the MSA

  • Link Training Bypass and Short Link Training modes

  • Lane Reversal Compile Time SV Parameter Based Support

  • Scrambling Bypass

  • Support for Image File Dumping

  • Support for Showing the Image data from the Received or Sent Frames in a GUI window

  • Support for the Single-Stream Transport (SST) mode

  • Support for the following Secondary Data Packet (SDP) types in the SST mode:

    • Adaptive-Sync SDP

    • Audio_CopyManagement SDP

    • CTA-861-G Audio InfoFrame SDP

    • Audio_Stream SDP

    • Audio_TimeStamp SDP

    • Camera SDP

    • Extension SDP

    • International Standard Recording Code (ISRC) SDP

    • Picture Parameter Set (PPS) SDP

    • Video Stream Configuration (VSC) SDP

    • Video Stream Configuration Extension for CTA InfoFrame (VSC_EXT_CTA) SDP

    • Video Stream Configuration Extension for VESA (VSC_EXT_VESA) SDP

  • Support for the Error Correction Code (ECC) checksum for the SDP

Supported interfaces:

  • C++

Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Source Sink Repeater
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification