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AVIP for AMBA CHI

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA CHI is a set of ready-made Verification IP for the Arm® AMBA® Coherent Hub Interface (CHI). It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium platform.

The AMBA CHI architecture enables you to connect multiple SoC on-die nodes using a scalable interconnect. The nodes on the interconnect can be as varied as cores, core clusters, I/O bridges, memory controllers, and graphics processors.

It is a directory-based coherence protocol, in which reads and writes are processed through a protocol node called the Home Node (HN). Home Nodes, if required, send snoops to caches in the system and collect corresponding snoop responses.

These are scalable to a large number of nodes.

Specification Support

All AMBA CHI transactions are in accordance with the Arm AMBA CHI Specification.

Product Highlights

Per the CHI protocol:

  • Packet-based communication

  • A layered protocol approach

  • A request-response protocol

  • Peer-to-peer communication

The AVIP for AMBA CHI can:

  • Drive CHI bus traffic on the CHI RNF, CHI HN2SN

  • Respond to CHI bus traffic on the CHI SNF, CHI HN2RNF

  • Repeat a transaction multiple times with the ability to change a part of the transaction attributes according to a specific pattern as a CHI RNF with the C++ interface

The AVIP for AMBA CHI supports:

  • CHI specification:

    • Issue A, B, C, D, E with CHI RNF, RNI, performance monitors, and passive components

    • Issue A, B, C, D with CHI SNF
    • Issue A, B, C, D with CHI HN2RNF
    • Issues A, B with other components
  • Packet or Flit mode of operation
    • Packet mode with CHI RNF

    • Packet mode with CHI SNF with support up to CHI D
    • Packet mode with CHI HN2RNF with support up to CHI D
    • Flit mode with all CHI components
  • All CHI transactions types including:

    • Snoop transactions
    • Cache maintenance transactions
    • Distributed Virtual Memory (DVM) transactions
    • Barrier transactions
  • Embedded cache model for CHI RNF

  • Data width of 128, 256, and 512

  • Support for Multiple Outstanding Transactions in RNF, SNF and HN2RNF

  • Support for Link layer credit controls—maximum credit, minimum credit delay, and maximum credit delay
The AVIP for CHI Issue E with RNF and RNI supports:
  • The MakeReadUnique, WriteEvictOrEvict, and Write Zero with no Data transactions
  • The Exclusive Read Transaction and the MakeReadUnique with Exclusive accesses enhancements
  • Interface behavior of Extending TxnID Width and Group ID extension
  • Arm architecture related to Memory Tagging

Supported interfaces:

  • C++
  • TLM2
  • UVM SystemVerilog

Supported flows:

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow.

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Documentation

  • AMBA CHI Accelerated VIP User Guide

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