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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA CHI is a set of ready-made Verification IP for the Arm® AMBA® Coherent Hub Interface (CHI). It enables tests to be run in a pure simulation environment, with the Cadence Incisive®Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP platform.

The AMBA CHI architecture enables you to connect multiple SoC on-die nodes using a scalable interconnect. The nodes on the interconnect can be as varied as cores, core clusters, I/O bridges, memory controllers, and graphics processors.

It is a directory-based coherence protocol, in which reads and writes are processed through a protocol node called the Home Node (HN). Home Nodes, if required, send snoops to caches in the system and collect corresponding snoop responses.

These are scalable to a large number of nodes.

Specification Support

All AMBA CHI transactions are in accordance with the Arm AMBA CHI Specification.

Product Highlights

Per the CHI protocol:

  • Packet-based communication

  • A layered protocol approach

  • A request-response protocol

  • Peer-to-peer communication


  • Supports flit control using the UVM SystemVerilog interface

  • Supports the Snoop transactions using the C++ interface

  • Supports the Snoop transactions in flit mode, using the UVM SystemVerilog interface

  • Supports CHI Issue B in both packet and flit control for the RNF, using the C++ interface

  • Supports CHI Issue B in flit mode, using the UVM SystemVerilog interface

  • Supports all CHI transactions, using AMBA-PV extension with the TLM2 interface including:

    • Snoop transactions
    • Cache maintenance transactions
    • Distributed Virtual Memory (DVM) transactions
    • Barrier transactions
  • Drives CHI bus traffic on the CHI RNF, CHI HN2SN

  • Responds to CHI bus traffic on the CHI SNF, CHI HN2RNF

  • Supports DATA_WIDTH: 128/256/512

  • Supports all CHI transactions, using the UVM SystemVerilog or C++ interface

  • Supports the following TLM2 transactions (without using AMBA-PV):

    • WriteNoSnpPtl
    • ReadNoSnp
  • Supports the following BFMs:

    • cdn_chi_rnf
    • cdn_chi_hn2rnf
    • cdn_chi_hn2sn
    • cdn_chi_rni
    • cdn_chi_snf
    • cdn_chi_b_rnf
    • cdn_chi_b_rni 
    • cdn_chi_b_hn2rnf
    • cdn_chi_b_snf_stb

Supported interfaces:

  • C++
  • TLM2
  • UVM SystemVerilog

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow.

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only