Fully AXI-compatible components to drive and respond to AXI bus trafficFully AXI-compatible components to drive and respond to AXI bus trafficFully AXI-compatible components to drive and respond to AXI bus traffic

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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA AXI is a set of ready-made, highly configurable Verification IP for the Arm® AMBA® AXI interface. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for AMBA AXI is a complementary product to the Cadence VIP for AMBA AXI, and enables simulation acceleration and virtual emulation with the C++, TLM2, or UVM SystemVerilog environment, for subsystem- and system-level verification.

Specification Support

All AMBA AXI transactions are in accordance with the following Arm specifications:

Product Highlights

  • Generate and drive bus traffic as an AXI Master
  • Respond to bus traffic as an AXI Slave
  • Collect protocol coverage at the burst abstraction level when used with the UVM SystemVerilog testbench
  • Monitor the bus traffic at burst abstraction level as an AXI passive (currently, the support is available for the C/C++ and UVM SystemVerilog interfaces)
  • Repeat a transaction multiple times with the ability to change a part of the transaction attributes according to a specific pattern. (Currently, the AXI Master AVIP supports it using the C++ interface.)

The AVIP for AMBA AXI supports all types of AXI transactions, including:

  • Unaligned transfers
  • Narrow transfers
  • Receipt of interleaved transactions
  • Outstanding transactions
  • Receipt of out-of-order transactions
  • Data-before-address
Supported interfaces:
  • C++
  • TLM2
  • UVM SystemVerilog
Supported flows:
legacy ICE -vavlog vaelab


For embedded AMBA Slaves

For embedded AMBA Slaves

For embedded AMBA Slaves

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification


  • AMBA AXI Accelerated VIP User Guide

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