Home: IP Portfolio > Verification IP > Accelerated VIP > AVIP for AMBA AXI

AVIP for AMBA AXI

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA AXI is a set of ready-made, highly configurable Verification IP for the Arm® AMBA® AXI interface. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP Verification Computing Platform.

The AVIP for AMBA AXI is an extension of the Cadence VIP for AMBA AXI, and enables you to either move from simulation with the VIP for AMBA AXI to—or create a new C++ or TLM2 environment for—simulation acceleration.

Specification Support

All AMBA AXI transactions are in accordance with the following Arm specifications:

  • AMBA AXI and ACE Protocol Specification for AXI3, AXI4, and AXI4-Lite
  • AMBA AXI and ACE Protocol Specification for AXI5

Product Highlights

  • Generate and drive bus traffic as an AXI Master
  • Respond to bus traffic as an AXI Slave
  • Collect protocol coverage at the burst abstraction level when used with an e testbench
  • Monitor the bus traffic at burst abstraction level as an AXI passive (Currently, the support is available for the C/C++ and UVM SystemVerilog interfaces)
The AVIP for AMBA AXI supports all types of AXI transactions, including:
  • Unaligned transfers
  • Narrow transfers
  • Receipt of interleaved transactions
  • Outstanding transactions
  • Receipt of out-of-order transactions
  • Data-before-address
Supported interfaces:
  • C++
  • TLM2
  • UVM e
  • UVM SystemVerilog
Supported flows:
  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow
  • In-circuit emulation with the Palladium XP platform—embedded AXI Slaves only; can be compiled using the IXCOM STB flow, the xeCompile legacy flow or the vavlog/vaelab legacy flow
  • Simulation acceleration with the Palladium III platform—AXI Master and embedded AXI Slaves only using the IXE COLS flow; Verilog modules must be compiled using BCU Compiler
    Verilog modules must be compiled using BCU Compiler and not IXE questQel. In addition, CTB is a mandatory flag for the BCU and irun phases.

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration HW/SW Co-Verification