Home: IP Portfolio > Verification IP > Accelerated VIP > AVIP for AMBA APB


The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA APB is a set of ready-made, highly configurable Verification IP for the Arm® AMBA® APB interface. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for AMBA APB is a complementary product to the Cadence VIP for AMBA APB, and enables simulation acceleration and virtual emulation with the C++, TLM2, or UVM SystemVerilog environment, for subsystem- and system-level verification.

Specification Support

  • All AMBA APB transactions are in accordance with the Arm AMBA APB Protocol Specification, Version 2.

Product Highlights

  • Generate and drive bus traffic as an APB master
  • Respond to bus traffic as an APB slave
  • Support batching mode in APB master
  • Support user-configurable delays on the APB bus in the C++ and UVM SystemVerilog interfaces

Supported Interfaces

  • UVM SystemVerilog
  • C++
  • TLM2

Supported Flows

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification