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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA APB is a set of ready-made, highly configurable Verification IP for the Arm® AMBA® APB interface. It enables tests to be run in a pure simulation environment, with the Cadence Incisive® Enterprise Simulator, or in simulation acceleration with the Incisive Enterprise Simulator and the Palladium XP Verification Computing Platform.

The AVIP for AMBA APB is an extension of the Cadence VIP for AMBA APB, and enables you to either move from simulation with the VIP for AMBA APB with the UVM SystemVerilog user interface to—or create a new C+ or TLM2 environment for—simulation acceleration.

Specification Support

  • All AMBA APB transactions are in accordance with the Arm AMBA APB Protocol Specification, Version 2.

Product Highlights

  • Generate and drive bus traffic as an APB master
  • Respond to bus traffic as an APB slave
  • Support batching mode in APB master
  • Support user-configurable delays on the APB bus in the C++ and UVM SystemVerilog interfaces

Supported Interfaces

  • UVM SystemVerilog
  • C++
  • TLM2

Supported Flows

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification