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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA AHB is a set of ready-made, highly configurable Verification IP for the Arm® AMBA® AHB interface. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for AMBA AHB is a complementary product to the Cadence VIP for AMBA AHB, and enables simulation acceleration and virtual emulation with the C++, TLM2, or UVM SystemVerilog environment, for subsystem- and system-level verification.

Specification Support

All AMBA AHB transactions are in accordance with the following Arm specifications:

  • AMBA Specification (Rev 2.0)
  • AMBA 3 AHB-Lite Protocol Specification v1.0
  • AMBA 5 AHB Protocol Specification

Product Highlights

  • Generate and drive bus traffic as an AHB master
  • Respond to bus traffic as an AHB slave
  • Support batching mode in AHB master
  • Support data bus widths of 32, 64, and 128 bits
  • The AHB master supports user-configurable idle and busy delays on the AHB bus
  • The AHB slave supports user-configurable wait state delays on the AHB bus
  • The AVIP for AHB Master supports all types of AMBA AHB transactions.
  • The AVIP for AHB Slave supports all types of AMBA AHB transactions, except for early burst termination.

Supported Interfaces

  • UVM SystemVerilog
  • C++
  • TLM2

Supported Flows

  • Simulation acceleration with the Palladium platform, compiled using the IXCOM flow

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification