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The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

The AVIP library for AMBA ACE is a set of ready-made, highly configurable Verification IP for the Arm® AMBA® ACE interface. It enables tests to be run in a pure simulation environment, with the Cadence Xcelium simulator, or in simulation acceleration with the Xcelium simulator and the Palladium Verification Computing Platform.

The AVIP for AMBA ACE is a complementary product to the Cadence VIP for AMBA ACE, and enables simulation acceleration and virtual emulation with the C++, TLM2, or UVM SystemVerilog environment, for subsystem- and system-level verification.

Specification Support

All AMBA ACE transactions are in accordance with the following Arm specifications:

Product Highlights

  • Generate and drive bus traffic as an ACE master
  • Respond to bus traffic as an ACE slave
  • Repeat a transaction multiple times with the ability to change a part of the transaction attributes according to a specific pattern. (Currently, the ACE Master AVIP supports it using the C++ interface.)

Other Supported Features

The AVIP for AMBA ACE supports all types of ACE transactions, including:

  • Barrier transactions
  • Cache maintenance transactions
  • Distributed Virtual Memory (DVM) transactions
  • Snoop transactions
  • Receipt of out-of-order transactions
  • Data-before-address

Supported interfaces:

  • C++
  • TLM2
  • UVM SystemVerilog

Supported flows:

PXP Legacy ICE—xeCompile
PXP Legacy ICE—vavlog, vaelab
Yes For embedded AMBA Slaves For embedded AMBA Slaves For embedded AMBA Slaves

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Usage Options

Simulation Acceleration HW/SW Co-Verification