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Accelerated VIP

Accelerated VIP supports hardware acceleration of SoC interfaces such as USB, PCI Express, Ethernet, MIPI, AMBA AXI, AMBA AHB, and AMBA ACE

Speeding Verification on Hardware Accelerators

Sometimes chips are just too big to verify with logic simulation software. SoCs comprised of tens of millions of logic gates will bog down software simulators, even when running on the fastest servers. 

Simulating big designs requires hardware-assisted verification, an approach that uses special-purpose hardware, like Cadence® Palladium® XP systems, to dramatically boost simulation performance. Just as simulation VIP simplifies traditional logic simulation, Accelerated VIP makes hardware-assisted verification easier and more productive. 

Cadence Accelerated VIPs are complementary products to Cadence simulation VIP and SpeedBridges. Accelerated VIPs are used to funnel data to the user’s design-under-test and respond to stimulus received from it.  Monitor functions such as collecting coverage and setting callbacks are not included.

Tuned for performance, AVIPs are an integral component in a simulation acceleration environment, speeding up verification 10’s to 1,000’s of times relative to simulation. The level of acceleration gain is dependent on the user’s individual testbench and DUT synchronizations.

Usage Options

Cadence Accelerated VIP enable two popular methods of hardware-assisted verification: simulation acceleration and HW/SW co-verification.

Simulation Acceleration

In simulation acceleration, the Cadence Palladium XP system works in conjunction with the Cadence Xcelium™ Simulator to divide up the simulation task. The Palladium XP runs the design under test while the Xcelium simulator runs the testbench. Accelerated VIP is inserted for each of the standard interfaces in the design with the testbench interface running on Incisive and the acceleration-optimized core running on the Palladium XP.

Accelerated VIP is optimized for performance and can support a subset of simulation VIP capabilities. For instance, it generates all possible legal transactions and scoreboarding monitors are included with the UVM Active Agents. Certain performance-limiting features may not be available.

HW/SW Co-Verification

With the HW/SW co-verification approach, both the test environment and the design under test run in the Palladium XP system. This results in huge performance gains – typically 10,000X to 100,000X faster than logic simulation. That kind of speed enables the verification of software along with the hardware design. This enables hardware/software integration bugs to be efficiently discovered and fixed – a task that would be nearly impossible to manage otherwise. To facilitate the HW/SW co-verification approach, application software is often used to run tests and monitor results.

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More Information

ARM® AMBA® Boost simulation performance for AMBA-based designs

AVIP for AMBA AXIGenerate and drive bus traffic as an AXI master

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Display Visualize full frame images and videos

HDMI 1.4 Accelerated VIPSupports all extended resolution frames, including 3D

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HDMI 2.0 Accelerated VIPSupports all extended resolution frames, including 3D

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Ethernet Test billions of network transactions

AVIP for EthernetEnable design acceleration using the Cadence Palladium® XP

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AVIP for Ethernet 40G/100GRun tests in a pure simulation environment or in simulation acceleration with IES

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MIPI Accelerate performance for mobile designs

AVIP for MIPI CSI-2Fully configurable CSI-2 packets in peripheral mode

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AVIP for MIPI DBIType-B and Type-C interface support

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AVIP for MIPI DSI-2Fully configurable DSI packets in host mode

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Other Speed verification of popular interfaces

AVIP for I2SConfigurable to I2S transmitter or I2S receiver

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AVIP for KeypadSupports 8x8 KEYPAD matrix

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AVIP for USB 2.0Configurable T0/T1 protocol parameters

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AVIP for SATA 1.5/3/6GSupport for PTO & DMA read/write and Non-data & Queued DMA ATA commands

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AVIP for SIMCARDConfigurable T0/T1 protocol parameters

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AVIP for USB 3.0Configurable T0/T1 protocol parameters

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PCI Express Accelerate verification of high-bandwidth interfaces

AVIP for PCIe 4.0Configurable T0/T1 protocol parameters

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AVIP for PCIe 2.0/3.0Configurable T0/T1 protocol parameters

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AVIP for CCIX Configurable T0/T1 protocol parameters

The Cadence® Accelerated Verification IP (AVIP) enables design acceleration using the Cadence Palladium® XP Verification Computing Platform, and supports a variety of use modes to enable both validation of systems and subsystems, as well as more extensive protocol compliance verification of block- and IP-level designs.

Specification Support

All CCIX transactions are in accordance with the Cache Coherent Interconnect for Accelerators (CCIX) specification.

Product Highlights

  • Supports generating CCIX transactions from multiple CCIX agents

  • CCIX transactions are converted to PCI Express® (PCIe®) vendor-defined messages (Compliant Header),  and sent over a PCIe Link
  • Supports both RNF and HNF agent types
  • Supports an internal cache for HNF agents, with an option to automatically respond from the cache
  • Supports an internal Memory for RNF agents, with an option to automatically respond from the memory

  • All CCIX transaction types (except for the ones listed in the Limitations of the CCIX AVIP)
  • Automatic credit handling
  • Multiple RNF/HNF agents on top of a single PCIe link

Supported interfaces:

  • UVM SystemVerilog

Supported flows:

  • Simulation acceleration with the Palladium XP platform, compiled using the IXCOM flow.

Verilog modules must be compiled using BCU Compiler and not IXE questQel. In addition, CTB is a mandatory flag for the BCU and irun phases.


  • For UVM SystemVerilog back-to-back configuration and example, see <VIPCAT_install_dir>/tools/denali_64bit/ddvapi/sv/uvm/ccix/examples_avip

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only