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Accelerated VIP

Accelerated VIP supports hardware acceleration of SoC interfaces such as USB, PCI Express, Ethernet, MIPI, AMBA AXI, AMBA AHB, and AMBA ACE

Speeding Verification on Hardware Accelerators

Sometimes chips are just too big to verify with logic simulation software. SoCs comprised of tens of millions of logic gates will bog down software simulators, even when running on the fastest servers. 

Simulating big designs requires hardware-assisted verification, an approach that uses special-purpose hardware, like Cadence® Palladium® XP systems, to dramatically boost simulation performance. Just as simulation VIP simplifies traditional logic simulation, Accelerated VIP makes hardware-assisted verification easier and more productive. 

Cadence Accelerated VIPs are complementary products to Cadence simulation VIP and SpeedBridges. Accelerated VIPs are used to funnel data to the user’s design-under-test and respond to stimulus received from it.  Monitor functions such as collecting coverage and setting callbacks are not included.

Tuned for performance, AVIPs are an integral component in a simulation acceleration environment, speeding up verification 10’s to 1,000’s of times relative to simulation. The level of acceleration gain is dependent on the user’s individual testbench and DUT synchronizations.

Usage Options

Cadence Accelerated VIP enable two popular methods of hardware-assisted verification: simulation acceleration and HW/SW co-verification.

Simulation Acceleration

In simulation acceleration, the Cadence Palladium XP system works in conjunction with the Cadence Xcelium™ Simulator to divide up the simulation task. The Palladium XP runs the design under test while the Xcelium simulator runs the testbench. Accelerated VIP is inserted for each of the standard interfaces in the design with the testbench interface running on Incisive and the acceleration-optimized core running on the Palladium XP.

Accelerated VIP is optimized for performance and can support a subset of simulation VIP capabilities. For instance, it generates all possible legal transactions and scoreboarding monitors are included with the UVM Active Agents. Certain performance-limiting features may not be available.

HW/SW Co-Verification

With the HW/SW co-verification approach, both the test environment and the design under test run in the Palladium XP system. This results in huge performance gains – typically 10,000X to 100,000X faster than logic simulation. That kind of speed enables the verification of software along with the hardware design. This enables hardware/software integration bugs to be efficiently discovered and fixed – a task that would be nearly impossible to manage otherwise. To facilitate the HW/SW co-verification approach, application software is often used to run tests and monitor results.

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ARM® AMBA® Boost simulation performance for AMBA-based designs

AVIP for AMBA ACEFully ACE-compatible components to drive and respond to ACE bus traffic

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AVIP for AMBA AHBFully AHB-compatible components to drive and respond to AHB bus traffic

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AVIP for AMBA APB Fully APB-compatible components to drive and respond to APB bus traffic

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AVIP for AMBA AXIFully AXI-compatible components to drive and respond to AXI bus traffic

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AVIP for AMBA CHIFully configurable CHI packets, RN, SN and HN component configurations

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Display Visualize full frame images and videos

AVIP for HDMI 1.3/1.4 Supports all extended resolution frames, including 3D

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AVIP for HDMI 2.0Supports all extended resolution frames, including 3D

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Ethernet Test billions of network transactions

AVIP for Ethernet 1G/10GSupports MAC, PCS, PMA interfaces with configurable network traffic generation

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AVIP for Ethernet 25G/50GSupports MAC, PCS, PMA interfaces with configurable network traffic generation

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AVIP for Ethernet 40G/100GSupports MAC, PCS, PMA interfaces with configurable network traffic generation

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MIPI Accelerate performance for mobile designs

AVIP for MIPI CSI-2Fully configurable CSI-2 packets in RX or TX modes

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AVIP for MIPI DBIType-B and Type-C interface support

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AVIP for MIPI DSIFully configurable DSI packets in Peripheral or Host modes

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AVIP for MIPI DSI-2 Fully configurable DSI packets in Peripheral or Host modes

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Other Speed verification of popular interfaces

AVIP for CCIXFully configurable CCIX packets

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AVIP for I2CFully configurable I2C packets

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AVIP for I2SConfigurable to I2S transmitter or I2S receiver, with various number of channels

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AVIP for KeypadSupports 8x8 KEYPAD matrix

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AVIP for SATA 1.5/3/6GSupport for PIO and DMA read/write, non-data and queued DMA ATA commands

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AVIP for SIMCARDConfigurable T0/T1 protocol parameters

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AVIP for USB 2.0Hi-Speed and OTG 1.3

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AVIP for USB 3.0SuperSpeed/Hi-Speed with Host, Device and OTG 2.0

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PCI Express Accelerate verification of high-bandwidth interfaces