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Accelerated VIP

Accelerated VIP supports hardware acceleration of SoC interfaces such as USB, PCI Express, Ethernet, MIPI, AMBA AXI, AMBA AHB, and AMBA ACE

Speeding Verification on Hardware Accelerators

Sometimes chips are just too big to verify with logic simulation software. SoCs comprised of tens of millions of logic gates will bog down software simulators, even when running on the fastest servers. 

Simulating big designs requires hardware-assisted verification, an approach that uses special-purpose hardware, like Cadence® Palladium® XP systems, to dramatically boost simulation performance. Just as simulation VIP simplifies traditional logic simulation, Accelerated VIP makes hardware-assisted verification easier and more productive. 

Cadence Accelerated VIPs are complementary products to Cadence simulation VIP and SpeedBridges. Accelerated VIPs are used to funnel data to the user’s design-under-test and respond to stimulus received from it.  Monitor functions such as collecting coverage and setting callbacks are not included.

Tuned for performance, AVIPs are an integral component in a simulation acceleration environment, speeding up verification 10’s to 1,000’s of times relative to simulation. The level of acceleration gain is dependent on the user’s individual testbench and DUT synchronizations.

Usage Options

Cadence Accelerated VIP enable two popular methods of hardware-assisted verification: simulation acceleration and HW/SW co-verification.

Simulation Acceleration

In simulation acceleration, the Cadence Palladium XP system works in conjunction with the Cadence Xcelium™ Simulator to divide up the simulation task. The Palladium XP runs the design under test while the Xcelium simulator runs the testbench. Accelerated VIP is inserted for each of the standard interfaces in the design with the testbench interface running on Incisive and the acceleration-optimized core running on the Palladium XP.

Accelerated VIP is optimized for performance and can support a subset of simulation VIP capabilities. For instance, it generates all possible legal transactions and scoreboarding monitors are included with the UVM Active Agents. Certain performance-limiting features may not be available.

HW/SW Co-Verification

With the HW/SW co-verification approach, both the test environment and the design under test run in the Palladium XP system. This results in huge performance gains – typically 10,000X to 100,000X faster than logic simulation. That kind of speed enables the verification of software along with the hardware design. This enables hardware/software integration bugs to be efficiently discovered and fixed – a task that would be nearly impossible to manage otherwise. To facilitate the HW/SW co-verification approach, application software is often used to run tests and monitor results.

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More Information

ARM® AMBA® Boost simulation performance for AMBA-based designs

AMBA 4 ACE Accelerated VIPSpeed verification of multi-core designs

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AMBA AXI Accelerated VIPGenerate and drive bus traffic as an AXI master

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AMBA AHB Accelerated VIPSupport data bus widths of 32, 64, and 128 bits

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AMBA APB Accelerated VIPRespond to bus traffic as an APB slave

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Display Visualize full frame images and videos

HDMI 1.4 Accelerated VIPSupports all extended resolution frames, including 3D

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HDMI 2.0 Accelerated VIPSupports all extended resolution frames, including 3D

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Ethernet Test billions of network transactions

Ethernet 10/100/1G/10G Accelerated VIPEnable design acceleration using the Cadence Palladium® XP

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Ethernet 40G/100G Accelerated VIPRun tests in a pure simulation environment or in simulation acceleration with IES

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MIPI Accelerate performance for mobile designs

MIPI CSI-2 Accelerated VIPFully configurable CSI-2 packets in peripheral mode

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MIPI DBI Accelerated VIPType-B and Type-C interface support

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MIPI DSI Accelerated VIPFully configurable DSI packets in host mode

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Other Speed verification of popular interfaces

I2C Accelerated VIPFully configurable I2C packets

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I2S Accelerated VIPConfigurable to I2S transmitter or I2S receiver

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Keypad Accelerated VIPSupports 8x8 KEYPAD matrix

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SATA 3G/6G Accelerated VIPSupport for PTO & DMA read/write and Non-data & Queued DMA ATA commands

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SIMCARD Accelerated VIPConfigurable T0/T1 protocol parameters

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USB 2.0 Accelerated VIPConfigurable T0/T1 protocol parameters

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PCI Express Accelerate verification of high-bandwidth interfaces