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Tensilica Reference Configurations

Tensilica processors excel in high performance, low power processingChoosing the Ideal Processor for Your Next SoC Design

Are you looking for the Tensilica Diamond Standard Controllers?

The Tensilica 'Diamond Standard Controllers' are no longer available as licensible products in the Tensilica portfolio. For customers looking to build processors with similar feature sets to the diamond controllers, we have a set of reference configurations that can be used as a starting point. The reference configurations can be downloaded and used as a starting point with a Tensilica processor license.  

Since the Diamond Controllers were discontinued, we have made several generations of improvements to the Xtensa Processor Platform. This means you can build smaller, lower power and higher performance equivalents to the original Diamond standard controllers. 

The pre-configured processor templates are designed to address different embedded processing use cases from a small embedded controller to a high-performance 4-issue real-time processor. They make it easy to choose a starting point that is closest to what's required for your embedded application. They can be used as-is, or further optimized to create the ideal processor for your application.

Diamond Controller and Reference Configuration Comparison Table 

The table below is a guide to help you choose the best reference configuration as the starting point for each of the original 'Diamond Standard Controllers'. 

Diamond Controller Reference Configuration Comments
106Micro XRC_5C2

Configuration to use as a starting point for your Tensilica processor

212GP XRC_5C4
570T XRC_5C6
Application Specific Diamond Go to Application Page Comments
330HiFi HiFi DSP for Audio/Voice/SpeechAudio
Application Specific DSPs
545CK ConnX DSP for Communications/Baseband 


Embedded Control Features of Tensilica Processors 

Based on the Proven Xtensa Architecture

Today's complex SoCs include numerous specialized functions and also deeply embedded control tasks. Tensilica processors excel at deeply embedded control tasks as well as application specific tasks like computer vision, audio, communications and speech processing. For those application specific tasks there are industry leading specialized Tensilica DSP processors ready to integrate now - check out the bottom of this page.

All Tensilica processors (including the Reference configurations) are based on the 32-bit RISC Xtensa Instruction Set Architecture (ISA), with 80 common base instructions, a 32-bit ALU; 16, 32 or 64 general-purpose registers; and six special purpose registers. The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions. These 16- and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance.

Tensilica processors can issue multiple instructions at once using the wider FLIX (similar to VLIW), when it's efficient to do so. These 2- to 4-issue instructions are modelessly intermixed with the 16- and 24-bit instructions without causing code bloat.

Rich Controller Feature Set

All Reference configurations are pre-configured with a minimal number of interrupts that can be increased if needed. Up to nine external interrupts at different hardware-defined priority levels are available to provide system flexibility. Additionally, three timer interrupts and two software interrupts are available. For extreme time-critical applications, a non-maskable interrupt is included.

Ideal in Low-Power Applications

Tensilica processors use clock gating, data gating and other architectural enhancements to keep power as low as possible. Clock and data gating stops unnecessary clocking activity to parts of the processor that are not in use on a particular clock cycle.

Support for Power Shut-Off (PSO) allows parts of the processor to be turned off when not being used to reduce leakage power.

The Loop Buffer allows the processor to run out of a small, low power instruction store rather than accessing the higher power local cache when running tight loops.

System Bus

Our system bus interface is configurable and capable of receiving inbound requests from an external master such as a DMA, with sophisticated system bus features like split-transactions and multiple outstanding requests.

You have three system bus choices:

  1. No system bus—For deeply embedded, low cost designs
  2. AMBA® 2.0 AHB-Lite—For fast integration into AMBA AHB-based designs
  3. AMBA 4.0 AXI bus bridge—For fast integration into AMBA AXI-based designs

Feature Comparison of Tensilica Reference Configurations

Which Reference Configuration is the Right Starting Point for Your Application?

We created the Tensilica reference configurations to help you get started quickly and easily. The configurations offer pre-configured starting points with a broad range of performance. These configurations can then be tailored using our Xplorer Processor Generator Tool, for creating the ideal processor for your application. Xplorer has simple click box choices for easy modification of the reference configurations to suit your application needs. 

Are the Tensilica Reference Configurations Licensable Products?

The Tensilica reference configurations are not individually licensable processor IP products, they are pre-configured starting points or templates for customers who have already licensed a Tensilica Xtensa based processor. They are designed to provide you with a choice of pre-configured processors, offering a range of use cases and performance choices. The selector guide below shows the differences in feature set of the reference configurations. 

Tensilica Reference Configuration Selector Guide

Pipeline stages (5 or 7) 5 5 5
Performance Efficiency - DMIPS/MHz 1.49 1.72 2.05
Performance Efficiency - CoreMarks/MHz 3.33 4.18 4.38
Core Area (28 HPM 9 track - mm2) 0.016 0.037 0.069
Dynamic Power (NOP) (28HPM 9T uW/MHz) 5.7 10.3 13.6
Dynamic Power (Dhrystone) (28HPM 9T uW/MHz) 9.6 17.3 27.6
Instruction width (up to 128-bits) 16/24/32 16/24/64 16/24/96
Multiple instruction issue Up to 2 Up to 3 Up to 4
General-purpose registers (up to 64) 16 32 64
Instruction cache size (up to 128Kb) - 32Kb 32Kb
I-Cache associativity - 2-way 2-way
Data cache size (up to 128Kb) - 32Kb 32Kb
D-Cache associativity (up to 4-way) - 2-way 2-way
Local instruction RAM (up to 4MB, 1 or 2 banks) 128Kb - -
Local data RAM (up to 4MB, 1 or 2 banks) 128Kb - -
Load / Store units 1 1 2
Divider (32bit integer) no no yes
Zero-overhead looping no yes yes
Interrupts (up to 32 with up to 6 priority levels) 2 2 2



Build Your Own—Customize Your Processor

Like the Xtensa Reference Configurations, But Want More?

Our reference configurations are regular Xtensa processors that have been pre-configured. Customers find that one of the reference configurations is close to what they need, but want just a little bit more (or a little bit less) of something. That's the beauty of our system.

You can start with a reference configuration and add what you want, or take away what you don't want, using our Xtensa processor generator development tools. Many options are simple click-box choices so it's really easy to change.

If you're not sure, just play around and see how adding or removing an option affects your software profile.

Check out our Xtensa processor section to see the wide set of options that are available to you right now.

Comprehensive Hardware and Software Design Tools

Our Proven, Comprehensive Hardware and Software Design Environment

Processor design process


For Processor Designers

Cadence delivers patented, proven tools that automate the process of generating a custom processor or DSP along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Cadence has the tools you need to create successful products.

View the complete set of tools for processor designers.

Software development process

For Software Developers

When you need to develop application code for a Tensilica processor, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. Cadence's Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.