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ConnX DSPs for Radar, Lidar, and Communications

Designed for your next generation products

Cadence offers more ways to perform complex signal processing than any other IP company. Cadence offers a wide range of DSPs for selecting the best combination of high performance, low power, and small area to meet the needs of your application.

From the dual or quad MAC Fusion F1 up to the super-high-performance 128-MAC ConnX B20, these Tensilica DSPs are designed for a broad range of applications that control sensors and antennas and process the data they handle. Go with the industry's lowest power, most compact and best performing DSPs for applications including radar, lidar, 5G, 4G/LTE-A, bluetooth, smartgrid, and 802.11 modems. Cadence offers several pre-designed, pre-verified DSPs so you can accelerate your design effort and shorten your time to market.

No matter which Tensilica processor solution you choose, remember that it's based on our 32-bit Xtensa® RISC processor and toolset. Unlike a traditional fixed-configuration DSP, all Tensilica DSPs and processors are fully:

  • Configurable—Multiple pre-verified vector packages to select from
  • Extensible—Customizable instruction set through the Verilog-like TIE language
  • Connected—Virtually unlimited bandwidth from customizable FIFO, GPIO, and lookup interfaces
  • Scalable—Software compatible DSP family, making evaluation/migration easy

Whether your need is for a single DSP, a homogeneous multi-core solution, or a highly optimized heterogeneous mix of processors, DSPs, and hardware accelerator blocks, our family of DSPs, is the ideal place to get started on your platform design.

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Radar and Lidar Applications

With the trend towards automated driving (AD), vehicle sensors are critical for safety. There are three main sensors required going forward: cameras, radar and lidar. Cameras use visible light and rely on any objects they wish to see being illuminated – see Tensilica Vision DSPs for more details. Radar and Lidar sensors emit (modulated) electromagnetic waves that reflect off objects and are then detected back at the sensor.

Radar sensors emit millimeter waves that work well in poor weather conditions and at long distances as the waves are not easily attenuated in the atmosphere. However, although they are small and low cost, today they are not able to produce a high-resolution image at a distance that can distinguish between multiple objects – something that lowers the safe speed for AD if relied upon for object detection. Radar manufacturers are now developing “imaging” or ”4D” radar solutions that provide much higher resolution from the use of more antennas and much more digital signal processing.

Lidar sensors emit nanometer waves (laser beams) and can distinguish between multiple objects at a distance with its shorter wavelength. However, the equipment today is too large and too expensive to be deployed in high volume autonomous vehicles. Lidar manufacturers are developing solid-state/MEMS sensors to reduce the size and cost, and putting all the digital signal processing needed into small, more power-efficient embedded systems.

The newest members of the software-compatible ConnX DSP family, the B20 and B10, have been designed specifically to meet the requirement for the new radar and lidar trends mentioned above, with the B20 providing up to 10X more performance compared to the popular BBE32EP in parts of the radar/lidar processing chain. With options for native vector 32-bit fixed point MACs (for FFT, FIR, Convolution and more), double single-precision floating point and the addition of half-precision floating point, designers have new choices for higher accuracy calculations and more parallelism along with a faster clock speed from a deeper processor pipeline for the higher performance processing and energy-efficiency needed.

5G Communication Applications

The benefits offered by 5G are very attractive for multiple use cases: for phone users getting more reliable and higher peak bandwidth for downloading movies; for machine to machine connections that can work in real-time; and for being able to connect thousands of devices at once without losing connection. These capabilities rely on the 5G infrastructure to be built-out by the operators first, and that is happening now with next generation products that work alongside the current 4G networks. These new 5G products can require 10X the processing performance for infrastructure and user equipment (UE). V2X and IoT don't need such high throughput, but they need lower latencies and the ability to connect huge numbers of devices at the same time. For all of these 5G markets, higher performance processing with energy-efficiency is needed that supports the new protocols. Even before the 5G infrastructure is there, UE smartphone manufacturers are releasing “5G-ready” phones in anticipation of the new networks being ready by the end of 2019 or into 2020, so new designs are already being developed.

The newest members of the software-compatible ConnX DSP family, the B20 and B10, have been designed specifically to meet the requirement for 5G, with the B20 providing up to 30X more performance compared to the popular BBE32EP in parts of the communication processing chain. With native vector 32-bit fixed point MACs (for FFT, FIR, convolution and more), FEC acceleration, double single-precision floating point and the addition of half-precision floating point, designers have new choices for higher accuracy calculations, software-defined V2X/IoT and more parallelism along with a faster clock speed from a deeper processor pipeline for the higher performance processing and energy-efficiency needed.

ConnX DSPs For Radar, Lidar, and 5G Applications

Software-Compatible DSPs For Radar, Lidar and 5G Applications

The Connx B20 DSP Architecture Block Diagram

The Cadence®Tensilica®ConnX family of enhanced digital signal processors (DSPs) establishes a new standard in high-performance, low-power digital signal processing specifically designed for radar, lidar, and communications processing. Optimized for complex number processing, the ConnX DSPs offer a wide range of software-compatible power, performance, and area (PPA) points to suit the needs of any application. These DSPs provide the scalability needed to deliver energy-efficient programmable solutions for radar, lidar, and communications applications (such as infrastructure, user equipment, IoT, and V2X). Easily optimized through check-box options, the ConnX DSPs provide unprecedented flexibility in implementing systems at power-consumption levels that significantly reduce the need for hardware accelerators. There are five members of this DSP family: BBE16EP, BBE32EP, BBE64EP, B10, and B20.

Instruction set features

THROUGHPUT / DSPBBE16EPBBE32EPBBE64EPB10B20
Vector/Memory Width (bits) 128 256 512 256 512
MAC 16-bit 16 32 64 64 128
MAC 32-bit - - - 16 32
SP FP FMA 4 8 16 16 32
HP FP FMA - - - 32 64
ALU 8-bit - - - 96 192
ALU 16-bit 24 48 96 48 96
ALU 32-bit 4 8 16 32 64
Divider 16-bit 1 2 4 2 4
Divider 32-bit - - - 1 2

Notes:
MAC: Multiply Accumulate operation. FMA: Fused Multiply-Add operation. ALU: Arithmetic Logic Unit. 
SP FP: Single-Precision Floating Point. HP FP: Half-Precision Floating Point

Features

  • Single-instruction, multiple-data (SIMD) vector processing
  • Up to 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
  • 32-bit scalar ALU
  • Higher precision for matrix inversion and divide operations
  • Advanced precision for matrix inversion and divide operations
  • Optimized instructions for:
    • 16-bit: Complex arithmetic
    • 16-bit: Polynomial evaluation
    • 16-bit: Matrix multiplication
    • 16-bit and SP: FFT and RECIP/RSQRT acceleration
    • 16-bit: FIR, convolution, correlation acceleration
    • 16-bit and 32-bit: Peak search acceleration
    • SP: Block floating-point
    • Bit-oriented operations
    • Vector compression and expansion
  • Predicated vector instructions
  • Vector single-precision floating-point option
  • For the B10 and B20 DSPs:
    • Faster clock speed compared to the ConnX BBE DSPs
    • 16-bit: sin/cos/complex exponent acceleration
    • Optional 32-bit vector fixed-point MAC: For FFT, FIR, convolution, correlation and more
    • Optional extended vector single-precision floating point: For 2X SP performance
    • Optional extended vector half-precision floating point
    • Optional communications acceleration: For forward error correction
  • High-performance C/C++ compiler with automatic vectorization of scalar C and full support for vector data
  • TI intrinsic support, rich application libraries
Load/store operations support five standard addressing modes and two specialized modes: bit reverse for FFTs and circular for functions like circular buffering. The addressing modes support a variety of data formats including scalar and vector, real, and complex data types.

Configurable, extensible, scalable

The ConnX DSPs provide pre-verified accelerator instruction options. These options are included/excluded as checkboxes when defining the processor and result in the seamless integration of that feature into the hardware, the compiler, the modeling tools, and the verification scripts. With these capabilities, you can build a custom DSP without the large development schedule impact that a change in hardware design would normally involve.

The ConnX DSPs can be extended to support custom ports and queues for efficient, direct, connection to offload accelerators and are fully supported in the programming and modeling tools. These custom interfaces can also be defined to match the interfaces of existing third-party IP. Thus, the ConnX DSPs can access hardware offload accelerators in a deterministic single- or multi-cycle operation, greatly reducing power consumption and without impacting the shared system bus.

Supported by a complete set of hardware and software tools

Optimized math libraries with source code and a common API are provided for all of these DSPs, along with example application code chains. Our complete set of tools includes a comprehensive instruction set simulator (ISS), which allows developers to quickly simulate and evaluate performance. The fast, functional TurboSimTM simulator option achieves speeds that are 40 to 80 times faster than the ISS for efficient software development and functional verification. System C and C-based system modeling can aid in full-chip simulations.

The tool set includes a high-performance C/C++ compiler with automatic vectorization and VLIW instruction bundling. This comprehensive tool set also includes the linker, assembler, debugger, profiler, and graphic visualization tools. All major EDA flows are supported. See our Knowledge Center for more information on our tools and the hardware/software development process

Learn more about Tensilica ConnX DSPs

Fusion F1 DSP For IoT, Wearables and Wireless Connectivity Applications

Flexible Fusion F1 DSP for Narrowband Wireless and IoT

No one processor can meet the varied demands of IoT, wearables, and wireless communications. That's why we developed the Cadence® Tensilica® Fusion F1 DSP, with the flexible options you need to mold the DSP into just what you need. 

This scalable DSP is ideal for applications requiring merged controller plus DSP computation, ultra-low energy and a small footprint. It can be designed into SoCs for wearable activity monitoring, indoor navigation, context-aware sensor fusion, secure local wireless connectivity, face trigger, voice trigger and voice recognition. Optional Instruction Set Architecture (ISA) extensions are included to accelerate multiple wireless protocols. The Fusion F1 DSP ISA also includes some Viterbi acceleration instructions, to speed up communication protocols using Viterbi algorithms.  

A Configurable Approach to Meet Your Needs

The Tensilica Fusion F1 DSP combines an enhanced 32-bit Xtensa control processor with market-leading DSP features and flexible algorithm-specific acceleration for a fully programmable approach, supporting multiple existing and developing standards as well as customer algorithms. For many IoT applications that are space- and energy-constrained, deploying a single, small, low-energy processor that can perform all of the programmable functions (sensor processing, wireless communications and control) is ideal.

IoT device designers can pick just the options they need using the Xtensa Processor Generator to produce a Tensilica Fusion F1 processor that can be smaller and more energy-efficient than a single one-size-fits-all processor while still having higher performance. 

A proven base architecture with lots of flexibility

The Tensilica Fusion F1 DSP offers low energy, high performance control and signal processing for a broad segment of IoT/wearable markets. This highly configurable architecture is specifically designed to excel at always-on processing - including wake-on-voice and sensor fusion applications - that require a merged controller plus DSP, ultra-low energy, and a small footprint. It can be designed into SoCs for wearable activity monitoring, indoor navigation, context-aware sensor fusion, face trigger, voice trigger, and voice recognition.

Additionally, the Tensilica Fusion F1 DSP is very efficient in running the narrowband wireless communications standards typically associated with IoT device communications, including protocols such as Bluetooth Low Energy, Thread and Zigbee using IEEE 802.15.4, SmartGrid 802.15.4g, Wi-Fi 802.11n and 802.11ah, 2G and LTE Category 0 release 12 and 13, and global navigation satellite systems (GNSS).

TENSILICA FUSION F1 BASE ARCHITECTURE
Feature Supported Benefits
VLIW Slots 2 Allows two concurrent operations
Fixed-point MACs per Cycle One 32x32
Two 24x24
Two 16x16 (four optional)
Flexible MAC architecture efficiently handles broad set of data types
Accumulator 64-bit
ITU/ETSI Intrinsics Yes Accelerates ITU/ETSI voice codec performance
Circular Buffer Yes Efficiently manage streams of data
Customer-defined Instructions for Further Optimization Yes Extend the ISA to efficiently meet customer requirements
Prefetch for Cache-based Configurations Optional Improves cache memory performance

DSP plus control

All Tensilica Fusion F1 DSPs are click-box additions to our customizable Xtensa® processor and include the base Xtensa instruction set. In other words, they are excellent targets for control applications as well.

Customizable to meet your requirements

Because our Tensilica Fusion F1 DSPs are based on our Xtensa processor, you get all of the customization advantages that our processors are known for, along with incredible flexibility, including (but not limited to):

  • Add/configure caches and local memories
  • Add direct RTL-like interfaces via Ports, Queues, and Lookup Interfaces
  • Add custom instructions with full compiler support

See our Xtensa product section for more details.

Optimized for always-on voice trigger and recognition

The Tensilica Fusion F1 DSP is our smallest, lowest power DSP supporting always-listening voice trigger and speech command modes. It enables a hands-free experience. Cadence is working with several software partners who provide innovative voice activation, speech command recognition, voice pre-processing and noise reduction products—all optimized on the Tensilica Fusion F1 DSP.

Fully programmable in C

The Tensilica Fusion F1 DSP is fully programmable in C, with no assembly required. So if you have proprietary algorithms to port, it’s easy and quick.

The features you need for applications ranging from ultra-low energy to high performance

Choosing a processor for IoT/wearable applications is a challenge. No one processor will be optimal for all IoT applications – one size does not fit all. In choosing a processor, it is desirable to have high configurability to scale the breadth of potential applications. It is also highly desirable that this processor architecture has very good DSP performance, both fixed and floating point, to process all of the sensor data available in these new devices. Finally, IoT/wearable processors need to be very energy efficient as many applications will be powered by small batteries, or rely on energy harvesting.

The Tensilica Fusion F1 DSP is based on the proven Xtensa Innovation Platform, which means it is highly configurable and you can add custom I/O and instructions to fit the needs of your application. In addition to the standard Xtensa processor configuration options, we've developed five optional blocks, tightly integrated with the main processor, to accelerate your design effort and help you customize the processor for your unique requirements.

Tensilica Fusion F1 IoT options

These five proven Tensilica Fusion F1 options for IoT applications include:

TENSILICA FUSION F1 OPTIONS
Option Benefits
Floating Point Unit
  • Single-precision
  • Floating point instructions issued concurrently with 64-bit load/store
  • Accelerates sensor processing algorithms
Audio/Voice/Speech (AVS)
  • Software compatibility with the HiFi DSP family
  • Access to over 170 HiFi audio/voice software packages
16-bit Quad MAC
  • Four 16x16 MACs
  • Accelerates communications standards like Bluetooth LE and Wi-Fi
  • Accelerates voice algorithm performance
AES (128 bit)
  • Encryption acceleration for narrowband wireless standards such as Bluetooth LE and Wi-Fi
Advanced Bit Manipulation
  • Accelerates performance of bit operations in baseband MAC/PHY processing

A strong partner ecosystem

Cadence has over 70 partners in its comprehensive ecosystem.. See the list on our Partners page. These companies, ranging from industry giants like Dolby and DTS to innovative companies for sensor fusion, always-on, sound enhancement, and noise reduction, have already ported their software to the Tensilica Fusion F1 DSP architecture so you don't have to. Get up and running very quickly with the software you need.

Learn more about Tensilica Fusion F1 DSPs

Datasheet

Fusion F1 DSP
Fusion G DSP Family

White Papers

Fixed- and Floating-Point FMCW Radar Signal Processing with Tensilica DSPs
Keeping Always-On Systems On for Low-Energy Internet-of-Things Applications
Managing Multiple Wireless Standards for Smart Home Applications
Meeting Multiple IoT Application Requirements with a Single, Configurable DSP Core

Videos

Chris Rowen highlights the requirements of the wide variety of sensors – environmental, motion, audio, and imaging. He'll cover data rates, sample rates, and levels of computation associated with sensors. He'll also discuss why, since computational requirements vary so much, a new DSP is needed. The Tensilica Fusion DSP uses a very flexible architecture that can be tailored for the computation required by whatever sensor you use.

 

Chris Rowen talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

 

Chris Rowen takes a look at the basic energy equation for processors and how a configurable processor architecture provides the flexibility to optimize power for a given application.

Press Release

New Tensilica Fusion DSP Sets Low-Energy Benchmarks for IoT, Wearables and Wireless Connectivity

 

Build Your Own DSPs

Customize your signal processing DSPs

See some interesting ideas, but want something slightly different? That's the beauty of the Cadence Tensilica approach to IP design. From the start, we designed our processor IP to be customizable. We used that same technology to create these innovative baseband DSPs.

Why Cadence?
  • Ultra-low power consumption and size—With optimized DSPs that reduce required system clock frequency
  • Flexibility—A scalable platform to fit all performance, power, and area budgets that can be further customized to meet your needs
  • Reduced development cost and development risk—All programmable in C, backed by a world-class development tool suite and multi-core support
  • Low-risk solution with a large ecosystem—Supports all Tensilica products
We recommend two approaches to get you quickly to the exact product you need:
  • Start with one of our standard ConnX products—Modifying an existing product will save you a lot of design work and effort
  • Start with our Tensilica processor—Starting with a clean slate means you can design everything just the way you'd like it

For digital signal processing (DSP) applications, with unique datapaths, processing requirements, algorithms, and memory requirements, this customization process is often essential to get the smallest, most energy-efficient core possible.

Either way, our automated tools will help you through the design process, making sure the design is correct by construction, and helping you make sure you get the right mix of power, performance, and area. And when you're done, our automated Xtensa processor generator will make sure you get not only the hardware for your new design, but also a complete matching software tool chain.

Accelerate hot spots in applications

You don't have to go to higher MHz to get higher performance. By adding instructions in TIE, our Verilog-like language, you can accelerate hot spots in your applications. You can pump data through our DSPs with up to two 512-bit-wide data load/stores per cycle, or bypass the bus entirely with our unique GPIO and FIFO Queues. Here are some ways you can customize our DSPs:

Data paths

  • The width of data load/store, computation execution, and register files can all be tailored to your specific application

SIMD widths

  • Some applications may greatly benefit from vectorizing computation through a SIMD machine
  • The size of SIMD and vector "strides" can be customized to optimum performance per power/area for the application

Custom instructions

  • Create instructions that perform application-specific tasks
  • Create "incredible performance" for application, reduce instruction memory footprint

Parallel instruction execution

  • VLIW architecture to enable parallel computation of instructions
  • Example: use one instruction to perform load, execute, store

Tools, Software, Libraries for DSPs

Tools, software, libraries—we have what you need to complete your design quickly

For digital signal processing (DSP) applications with unique datapaths, processing requirements, algorithms, and memory requirements, the Cadence customization process is often essential to get the smallest, most energy-efficient core possible. No matter what changes you make, you'll find our tools and software will help you be more efficient.

Hardware design 

For processor designers

Cadence delivers patented, proven tools that automate the process of generating a custom processor or DSP along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Cadence has the tools you need to create successful products.

View the complete set of tools for processor designers.

Software design

For software developers

When you need to develop your application software, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. The Cadence Tensilica Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.

Libraries

Libraries and existing DSP code base support

We do everything we can to make it was easy as possible to port your existing DSP code to our DSPs. Our Xtensa C/C++ Compiler efficiently maps C algorithms to our DSPs, no assembly coding required.

We also provide a range of DSP libraries already tailored to our products, so you can speed your design process.

Podcast

Articles

SemiWiki: Radar is Cheaper but Autonomous Car Needs Lidar!

eeNews: DSP IP boosts automotive radar/lidar performance

Embedded Control Europe: Cadence: Tensilica ConnX B20 DSP boosts performance by up to 30X for 5G communications

Embedded Computing Design: Cadence's Tensilica ConnX B20 DSP IP Boosts Performance for Automotive Radar/Lidar and 5G

Electronic Products: Tensilica DSP features a clock speed increase, optimized instructions