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Serial Peripheral Interface for SoC Designs | Cadence IP

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Serial Peripheral Interface (SPI)

Connect seamlessly to Cadence or third-party APB-compliant bus master devices and SPI peripherals. The Cadence® Serial Peripheral Interface (SPI) provides full-duplex, synchronous, and serial communication between master and slave, or other peripheral devices. 

Benefits

  • Full-duplex operation with simultaneous receive and transmit
  • Master or slave SPI modes of operation
  • Four-wire bus—data RX, data TX, clock, and select

The Cadence Serial Peripheral Interface (SPI) IP provides full-duplex, synchronous, and serial communication between master and slave, or other peripheral devices.

Supporting both master and slave interfaces, the Cadence Serial Peripheral Interface IP operates in single, and multi-master environments. FIFO depth and width is configurable to support virtually any protocol and throughput requirements.

Serial Peripheral Interface (SPI) Block Diagram

Features

  • Full-duplex operation, simultaneous receive and transmit
  • Separate transmit and receive FIFOs
  • Operates in master or slave mode