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Advanced Programmable Interrupt Controller (APIC)

Advanced Programmable Interrupt Controller (APIC) IP provides optimized interrupt management by reducing latency, and providing prioritized nesting of interrupts. It can process and control up to 32 interrupt sources. Of these, up to 31 are IRQ style interrupts and the remaining programmable source is fast interrupt (FIQ).

The Controller IP is compliant with the ARM® AMBA® 2 specification and designed to optimize interrupt handling performance providing a cost-effective solution for demanding multiprocessor computer system applications.


  • Low-risk solution, silicon-proven design
  • Programmable interrupt source type, all interrupts maskable
  • Easy integration with industry-standard ARM® AMBA® APB interface

The Controller IP generates coded interrupt requests from up to 32 software and hardware interrupt sources. The number of interrupt sources can be set at compile time to help reduce gate count.

Advanced Programmable Interrupt Controller (APIC) Block Diagram

Key Features

  • Programmable edge triggered (rising, falling) or sensitive (high, low) trigger source
  • Selectable source for fast IRQ
  • Supports up to 31 pending interrupt while servicing a single interrupt