Inter-IC Sound Bus Controller for SoC Designs | Cadence IP

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Inter-IC Sound Bus Controller (I2S)

A configurable single- or multi-channel Inter-IC Sound (I2S) bus interface controller, combines functions of both transmitter and receiver. The I2S IP can be used in various standard bus-based microprocessor systems, as various bus wrappers such as the ARM® AMBA® interface are provided. 


  • Meets Philips ® Inter-IC Sound Bus Specification
  • Supports various modes: I2S Philips Left or Right Justified, DSP, and time-division multiplexing (TDM)
  • Provides two clock domains: host side clock domain and system clock for the I2S channel

Cadence® Inter-IC Sound Bus Controller (I2S) IP includes both single-channel (I2S-SC) and multi-channel (I2S-MC) IP designs. It can be  targeted at ASIC and FPGA implementations, and used in a variety of different applications, such as connecting Analog-to- Digital and Digital-to-Analog converters with very low jitter, error correction for compact disc and digital recording, or digital signal processing. The Cadence Multi-Channel Inter-IC Sound Bus Controller IP can be used in user applications which require multiple channel audio data transmission, as well as in multimedia systems in general. 

Inter-IC Sound Bus Controller single-channel (I2S-SC) Block Diagram


Inter-IC Sound Bus Controller multi-channel (I2S-MC) Block Diagram


Key Features

  • Compliant with Philips Inter-IC Sound Bus Specification and ARM AMBA 2 Specification
  • With 32-bit data buses, the APB slave interface provides access to Special Function Registers and transmission FIFO memories
  • Ease-of-use design, customizable with easy integration