SD and eMMC PHY IP for SoC Designs | Cadence IP


Cadence offers separate PHY IP that covers the full range of SD/SDIO/eMMC™ speeds. Cadence SD 3.0, eMMC 5.1 PHY IP supports all SD legacy modes such as Default Speed, High Speed, and Ultra High Speed Phase I submodes (including SDR104 and DDR50), as well as JEDEC eMMC speeds including HS200, HS400, SDR, and DDR modes up to DDR52.

Our SD 3.0, eMMC 5.1 PHY IP facilitates implementation of the SD backend interface for SD cards and eMMC devices. This IP provides mechanisms that help meet timing requirements for the set of speed modes defined by the SD Physical Layer Standard Specification 3.0 and the JEDEC eMMC Standard (JESD84-B50).

Our SD 3.0, eMMC 5.1 quickly and easily integrates into a system on chip (SoC), and connects seamlessly to our SD/SDIO 3.0/eMMC 5.1 Host Controller IP and SD 4.0 Host Controller IP.

Silicon Library UHS-II PHY integrates with our SD 4.0 Host Controller IP using a standard LINK-PHY interface.


  • Easily configurable with optional SDR104, HS200, and HS400 modes
  • Faster time-to-market with early standards support
  • Wide standard support for system flexibility


  • SD 3.0, eMMC 5.1 PHY IP for SD/SDIO 3.0/eMMC 5.1 Host Controller, and SD 4.0 Host Controller legacy speed path