SD and eMMC PHY IP for SoC Designs | Cadence IP

PHY IP for SD and eMMC


  • Flexibility—Can be used for many flash interfaces
  • Simplicity—Using soft PHY simplifies SoC timing design
  • High performance—Allows up to 600MHz
  • Low-risk, proven design

Cadence offers separate PHY IP that covers the full range of SD/SDIO/eMMC speeds. Cadence PHY IP for SD 3.0 / eMMC 5.1 supports all SD legacy modes such as Default Speed, High Speed, and Ultra High Speed Phase I submodes (including SDR104 and DDR50), as well as JEDEC eMMC speeds including HS200, HS400, SDR, and DDR modes up to DDR52.

Our PHY IP for SD 3.0 / eMMC 5.1 facilitates implementation of the SD backend interface for SD cards and eMMC devices. This IP provides mechanisms that help meet timing requirements for the set of speed modes defined by the SD Physical Layer Standard Specification 3.0 and the JEDEC eMMC Standard (JESD84-B50).

Cadence PHY IP for SD 3.0 /eMMC 5.1 quickly and easily integrates into a system on chip (SoC), and connects seamlessly to our Host Controller IP for SD 4.0 UHS-I / eMMC 5.1.


  • Supports ONFI 4.1, Toggle 1, 2, xSPI, and eMMC5.1 devices and SD3.0 cards
  • Integrated DLL supports speeds up to 600MHz
  • Includes per-bit deskew mechanism
  • Fully digital soft PHY implementation
  • DFI 3.0 interface adopted for flash
  • Register interface for PHY programming
  • Loopback, DFT
  • DFI with 1:2 clock ratio support