SD and eMMC Host Controller IP for SoC Designs | Cadence IP

SD and eMMC Host Controller IP

Cadence SD/SDIO/eMMC Host Controller IP addresses your needs for embedded and removable storage in a wide range of applications. It is designed for low-power as well as high-performance systems, from measurement devices to smartphones, tablets, and cameras.

The SD/SDIO/eMMC Host Controller IP supports the latest Secure Digital (SD) specification and JEDEC eMMC standard. It offers many configuration options to fit particular design needs in terms of functionality and design constraints. Configurable features include type of DMA, number of slots, internal buffering scheme, speed modes supported, and type of on-­chip memory. Choose from more than 120,000 configurations to create an SD/SDIO/eMMC host controller for your specific requirements.

The SD/SDIO/eMMC Host Controller IP supports many features for low-power systems, including clock toggling disable. High-performance systems benefit from our advanced DMA engine (ADMA2) with scatter-gather operation. ADMA2 can read data from any number of different-sized locations within system memory without CPU interaction. For designs with silicon area constraints, we offer a single-operation DMA engine option, or you can choose to eliminate the DMA engine entirely.

For systems requiring connection to two or more components, our SD/SDIO/eMMC Host Controller IP supports a multi-slot feature for connecting up to four cards and devices. Any combination of components can be supported, including removable storage or memory cards, embedded eMMC-compliant devices, or extensible I/O such as GPS, Bluetooth®, or 3G cellular radios on SDIO cards.

Fully compatible with the SD host controller standard, our SD/SDIO/eMMC Host Controller IP works seamlessly with native OS drivers embedded in Linux, Microsoft Windows, and other operating systems.

The SD/SDIO 3.0 Host Controller IP supports Default Speed, High Speed, and Ultra High Speed Phase I (SDR12, SDR25, SDR50, SDR104, DDR50) modes for SD/SDIO devices. It also supports Backward Compatible mode, High Speed SDR, and High-­Speed DDR modes for eMMC devices. Cadence SD 4.0 Host Controller IP adds support for the latest Ultra High Speed Phase II (UHS-­II with FD156 and HD312) modes, for unsurpassed throughput with SD memory cards.

The eMMC 5.1 Controller IP supports HS200 and HS400 high speed modes for bandwidth of up to 400MB/s. In addition, the added Command Queuing Engine (CQE) improves smaller, random read-write operations, for higher system level IOs per second (IOPS).

Key Features

  • Supports SD memory, SD I/O cards, and eMMC devices
  • Complies with SD Specification Version 4.0 (Host and PHY) and JEDEC eMMC Standard 4.41
  • Supports Standard (SDSC), High (SDHC), and Extended (SDXC) capacity cards
  • Supports Default Speed, High Speed, Ultra High Speed Phase I, and Ultra High Speed Phase II modes 
  • Features optional SDMA and ADMA2 modules
  • Offers various system side interface options: OCP, ARM® AMBA® AHB™, AMBA AXI™
  • Up to 4 slots available
  • Supports 1-bit, 4-bit, and 8-bit card buses
  • Features ping-pong buffering with block size support up to 2048 bytes
  • Features tuning/retuning logic of sample clock


  • SD 3.0/SDIO 3.0/eMMC 5.1 Host Controller IP, a multi-slot host controller for SD 3.0 memory, SDIO 3.0 cards, and eMMC 5.1 devices
  • SD 4.0 Host Controller IP, a single-slot backward-compatible host controller for SD 4.0 memory cards, requires UHS-II PHY IP